Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanism, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain. This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed.

A survey of techniques for energy efficient on-chip communication

The Piezo-Electric Impedance Spectroscopy: Solutions and Applications. Piesoelektriline impedantsspektroskoopia: lahendused ja rakendused

Towards Adaptive Web - Analysing and Recommending Web Users’ Behaviour. Veebikasutajate käitumise analüüs ja soovitused adaptiivse veebi loomiseks

..................................................................................................... 98 KOKKUVÕTE .................................................................................................. 99 APPENDICES ................................................................................................. 101 Paper I ..................................................................................................... 103 Paper II ................................................................................................... 109 Paper III .................................................................................................. 115 CURRICULUM VITAE .................................................................................. 123 ELULOOKIRJELDUS .................................................................................... 125

Image Processing Solutions for Precise Road Profile Measurement Systems. Pilditöötluse lahendused täpsetele tee profiili mõõtesüsteemidele

........................................................................................... 86 KOKKUVÕTE ....................................................................................... 88 APPENDIX A ......................................................................................... 91 APPENDIX B ....................................................................................... 101 APPENDIX C ....................................................................................... 109 APPENDIX D ....................................................................................... 123 APPENDIX E ....................................................................................... 131 APPENDIX F ....................................................................................... 145 APPENDIX G ....................................................................................... 153 APPENDIX H ....................................................................................... 175 CURRICULUM VITAE ..................................................................... 183 ELULOOKIRJELDUS ....................................................................... 184

Flow-Sensitive Robotic Fish: From Concept to Experiments. Voolutundlik robotkala: ideest katsetusteni

System-Level Design of Timing-Sensitive Network-on-Chip Based Dependable Systems

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

System-Level Design of NoC-Based Dependable Embedded Systems

This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and synthesis approach for networks-on-chip where communication infrastructure is not able to provide communication interleaving (such as TDMA, virtual channels) or to guarantee communication delays. The idea is, to design a communication synthesis method, which would not be run off-chip as a CAD tool on a workstation, but on-chip and being activated whenever the system-on-chip (SoC) is re-configured.

Communication modelling and synthesis for NoC-based systems with real-time constraints

We are proposing a system level approach for a fault tolerant heterogeneous multi-processor system-on-chip (HMPSoC) platform that can be customized at design phase according to the requirements and the environmental constraints of the target application. This framework can provide optimal tradeoffs for maximizing the reliability of the system under real-time constraints. The proposed heterogeneous platform consists of a mesh-based network-on-chip (NoC) communication architecture, which is equipped with two different types of processing elements: (i) high fault tolerance (FT) and (ii) high performance (HP) processors. For critical applications, the designer can increase the proportion of fault tolerant processors in the HMPSoC in order to minimize the probability of failure by compromising the overall performance. Similarly, for less critical applications, the overall performance will increase by having a higher ratio of high performance processors. We will analyze the proposed HMPSoC architecture under different faults and performance constraints, so that the precise proportion of the diverse processors may be adjusted. The design space exploration has been carried out using our system-level design tool and the resulting schedules have been verified by executing the applications on cycle-accurate XHiNoC simulator. The objective of this approach is to generate a dependable system under hard real-time constraints with minimized hardware effort related to the adopted processing elements.

Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints

Communication modelling and synthesis plays an important role in the design of complex network-on-chip (NoC) based timing-sensitive systems-on-chip (SoC). To guarantee timing constraints without detailed know-how of communication might lead to unexpected results. In our previous work we have proposed an approach for communication modelling and synthesis to calculate communication hard deadlines that are represented by communication delay and guide the scheduling process to take into account possible network conflicts. In this paper we combine our communication scheduling approach with global optimisation techniques to perform design space exploration and/or improvement of the synthesised schedule.

Mihkel Tagel

Papers

System-Level Design of Timing-Sensitive Network-on-Chip Based Dependable Systems

System-Level Design of NoC-Based Dependable Embedded Systems

Communication modelling and synthesis for NoC-based systems with real-time constraints

Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints

Design space exploration and optimisation for NoC-based timing sensitive systems