Memristive devices, which combine a resistor with memory functions such that voltage pulses can change their resistance (and hence their memory state) in a nonvolatile manner, are beginning to be implemented in integrated circuits for memory applications. However, memristive devices could have applications in many other technologies, such as non–von Neumann in-memory computing in crossbar arrays, random number generation for data security, and radio-frequency switches for mobile communications. Progress toward the integration of memristive devices in commercial solid-state electronic circuits and other potential applications will depend on performance and reliability challenges that still need to be addressed, as described here. Description Putting memristors to work Memristors, which are resistors that change conductivity and act as memories, are not only being used in commercial computing but have several application areas in computing and communications. Lanza et al. review how devices such as phase-change memories, resistive random-access memories, and magnetoresistive random-access memories are being integrated into silicon electronics. Memristors also are finding use in artificial intelligence when integrated in three-dimensional crossbar arrays for low-power, non–von Neuman architectures. Other applications include random-number generation for data encryption and radiofrequency switches for mobile communications. —PDS A review explains how resistors with memory functions are being integrated into electronics and new computer architectures. BACKGROUND Memristive devices exhibit an electrical resistance that can be adjusted to two or more nonvolatile levels by applying electrical stresses. The core of the most advanced memristive devices is a metal/insulator/metal nanocell made of phase-change, metal-oxide, magnetic, or ferroelectric materials, which is often placed in series with other circuit elements (resistor, selector, transistor) to enhance their performance in array configurations (i.e., avoid damage during state transition, minimize intercell disturbance). The memristive effect was discovered in 1969 and the first commercial product appeared in 2006, consisting of a 4-megabit nonvolatile memory based on magnetic materials. In the past few years, the switching endurance, data retention time, energy consumption, switching time, integration density, and price of memristive nonvolatile memories has been remarkably improved (depending on the materials used, values up to ~1015 cycles, >10 years, ~0.1 pJ, ~10 ns, 256 gigabits per die, and ≤$0.30 per gigabit have been achieved). ADVANCES As of 2021, memristive memories are being used as standalone memory and are also embedded in application-specific integrated circuits for the Internet of Things (smart watches and glasses, medical equipment, computers), and their market value exceeds $621 million. Recent studies have shown that memristive devices may also be exploited for advanced computation, data security, and mobile communication. Advanced computation refers to the hardware implementation of artificial neural networks by exploiting memristive attributes such as progressive conductance increase and decrease, vector matrix multiplication (in crossbar arrays), and spike timing–dependent plasticity; state-of-the-art developments have achieved >10 trillion operations per second per watt. Data encryption can be realized by exploiting the stochasticity inherent in the memristive effect, which manifests as random fluctuations (within a given range) of the switching voltages/times and state currents. For example, true random number generator and physical unclonable functions produce random codes when exposing a population of memristive devices to an electrical stress at 50% of switching probability (it is impossible to predict which devices will switch because that depends on their atomic structure). Mobile communication can also benefit from memristive devices because they could be employed as 5G and terahertz switches with low energy consumption owing to the nonvolatile nature of the resistive states; the current commercial technology is based on silicon transistors, but they are volatile and consume data both during switching and when idle. State-of-the-art developments have achieved cutoff frequencies of >100 THz with excellent insertion loss and isolation. OUTLOOK Consolidating memristive memories in the market and creating new commercial memristive technologies requires further enhancement of their performance, integration density, and cost, which may be achieved via materials and structure engineering. Market forecasts expect the memristive memories market to grow up to ~$5.6 billion by 2026, which will represent ~2% of the nearly $280 billion memory market. Phase-change and metal-oxide memristive memories should improve switching endurance and reduce energy consumption and variability, and the magnetic ones should offer improved integration density. Ferroelectric memristive memories still suffer low switching endurance, which is hindering commercialization. The figures of merit of memristive devices for advanced computation highly depend on the application, but maximizing endurance, retention, and conductance range while minimizing temporal conductance fluctuations are general goals. Memristive devices for data encryption and mobile communication require higher switching endurance, and two-dimensional materials prototypes are being investigated. Part of Science’s coverage of the 75th anniversary of the discovery of the transistor Fundamental memristive effects and their applications. Memristive devices, in which electrical resistance can be adjusted to two or more nonvolatile levels, can be fabricated using different materials (top row). This allows adjusting their performance to fulfill the requirements of different technologies. Memristive memories are a reality, and important progress is being achieved in advanced computation, security systems, and mobile communication (bottom row).

Memristive technologies for data storage, computation, encryption, and radio-frequency communication

Memristor-type synaptic devices that can effectively emulate synaptic plasticity open up new directions for neuromorphic hardware systems. Here, a double high-k oxide structured memristor device (TaOx/HfO2) was fabricated, and its synaptic applications were characterized. Device deposition was confirmed through TEM imaging and EDS analysis. During the forming and set processes, switching of the memristor device can be divided into three types by compliance current and cycling control. Filamentary switching has strengths in terms of endurance and retention, but conductance is low. On the other hand, for interface-type switching, conductance is increased, but at the cost of endurance and retention. In order to overcome this dilemma, we proposed pseudo interface-type switching, and obtained excellent retention, decent endurance, and a variety of conductance levels that can be modulated by pulse response. The recognition rate calculated by the neural network simulation using the Fashion Modified National Institute of Standards and Technology database (MNIST) dataset, and the measured conductance values show that pseudo interface-type switching produces results that are similar to those of an interface-type device.

https://www.mdpi.com/2079-4991/10/8/1550/pdf

Pseudo-Interface Switching of a Two-Terminal TaOx/HfO2 Synaptic Device for Neuromorphic Applications.

To take advantages, such as multiplex capacity, non-photobleaching property, and high sensitivity, of surface-enhanced Raman scattering (SERS)-based in vivo imaging, development of highly enhanced SERS nanoprobes in near-infrared (NIR) region is needed. A well-controlled morphology and biocompatibility are essential features of NIR SERS nanoprobes. Gold (Au)-assembled nanostructures with controllable nanogaps with highly enhanced SERS signals within multiple hotspots could be a breakthrough.Au-assembled silica (SiO2) nanoparticles (NPs) (SiO2@Au@Au NPs) as NIR SERS nanoprobes are synthesized using the seed-mediated growth method. SiO2@Au@Au NPs using six different sizes of Au NPs (SiO2@Au@Au50-SiO2@Au@Au500) were prepared by controlling the concentration of Au precursor in the growth step. The nanogaps between Au NPs on the SiO2 surface could be controlled from 4.16 to 0.98 nm by adjusting the concentration of Au precursor (hence increasing Au NP sizes), which resulted in the formation of effective SERS hotspots. SiO2@Au@Au500 NPs with a 0.98-nm gap showed a high SERS enhancement factor of approximately 3.8 × 106 under 785-nm photoexcitation. SiO2@Au@Au500 nanoprobes showed detectable in vivo SERS signals at a concentration of 16 μg/mL in animal tissue specimen at a depth of 7 mm. SiO2@Au@Au500 NPs with 14 different Raman label compounds exhibited distinct SERS signals upon subcutaneous injection into nude mice.SiO2@Au@Au NPs showed high potential for in vivo applications as multiplex nanoprobes with high SERS sensitivity in the NIR region. 

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Highly sensitive near-infrared SERS nanoprobes for in vivo imaging using gold-assembled silica nanoparticles with controllable nanogaps

A positive-feedback (PF) neuron device capable of threshold tuning and simultaneously processing excitatory ( $G^{+}$ ) and inhibitory ( $G^{-}$ ) signals is experimentally demonstrated to replace conventional neuron circuits, for the first time. Thanks to the PF operation, the PF neuron device with steep switching characteristics can implement integrate-and-fire (IF) function of neurons with low-energy consumption. The structure of the PF neuron device efficiently merges a gated PNPN diode and a single MOSFET. Integrate-and-fire (IF) operation with steep subthreshold swing ( SS $n$ floating body of the PF neuron device. The carriers accumulated in the $n$ floating body are discharged by an inhibitory signal applied to the merged FET. Moreover, the threshold voltage ( $V_{\mathrm {th}}$ ) of the proposed PF neuron is controlled by using a charge storage layer. The low-energy consuming PF neuron circuit (~0.62 pJ/spike) consists of one PF device and only five MOSFETs for the IF and reset operation. In a high-level system simulation, a deep-spiking neural network (D-SNN) based on PF neurons with four hidden layers (1024 neurons in each layer) shows high-accuracy (98.55%) during a MNIST classification task. The PF neuron device provides a viable solution for high-density and low-energy neuromorphic systems.

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Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~1010), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications.

Understanding of Feedback Field-Effect Transistor and Its Applications

This letter presents a novel method for the sensitivity analysis between a process parameter and an electrical characteristic using the gradient of a neural network (NN). As devices become scaled and new emerging devices appear, it becomes more complex and the development of a SPICE model takes considerable time. Sensitivity analysis based on NN can accurately obtain the sensitivity even if the data are correlated with each other and have a non-linear relationship. The proposed method can be used to model the device characteristics and optimize process control through component analysis. It is verified using a feedback field-effect transistor (FBFET), one of the emerging neuromorphic devices. We execute experiments with 1055 TCAD simulations calibrated based on 33 measurement data for various process parameters and bias combinations and compare the results with a general linear model (GLM). In this work, we select 7 input parameters and extract voltage threshold ( ${V} _{\text {th}}$ ) and on-current ( ${I} _{\text {ON}}$ ), which are key characteristics of FBFET, as output parameters, and analyze the sensitivity with our method and provide a process control solution. This letter shows an important role in filling the gap between the emerging device proposal and the development of the SPICE model.

Sensitivity Analysis Based on Neural Network for Optimizing Device Characteristics

Spiking neural networks (SNNs) are considered as the third generation of artificial neural networks, having the potential to improve the energy efficiency of conventional computing systems. Although the firing rate of a spiking neuron is an approximation of rectified linear unit (ReLU) activation in an analog-valued neural network (ANN), there remain many challenges to be overcome owing to differences in operation between ANNs and SNNs. Unlike actual biological and biophysical processes, various hardware implementations of neurons and SNNs do not allow the membrane potential to fall below the resting potential-in other words, neurons must allow the sub-resting membrane potential. Because there occur an excitatory post-synaptic potential (EPSP) as well as an inhibitory post-synaptic potential (IPSP), negatively valued synaptic weights in SNNs induce the sub-resting membrane potential at some time point. If a membrane is not allowed to hold the sub-resting potential, errors will accumulate over time, resulting in inaccurate inference operations. This phenomenon is not observed in ANNs given their use of only spatial synaptic integration, but it can cause serious performance degradation in SNNs. In this paper, we demonstrate the impact of the sub-resting membrane potential on accurate inference operations in SNNs. Moreover, several important considerations for a hardware SNN that can maintain the sub-resting membrane potential are discussed. All of the results in this paper indicate that it is essential for neurons to allow the sub-resting membrane potential in order to realize high-performance SNNs.

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Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks.

‘Split-and-mix’ synthetic methods are widely utilized to prepare extensively large numbers of combinatorial libraries. For this, a simple and reliable encoding/decoding method is required to identify a lead compound, especially when it comes to combinatorial peptide/peptoid libraries. Here, we report a simple, efficient, and reliable on-bead peptoid ligand identification method using dual-modal identifiers (DM-IDs), which have a graphical pattern and a Raman signal. The DM-ID was designed to encode the sequence and the type of peptoid side chain by the number of holes and the surface-enhanced Raman scattering (SERS) signals, respectively. Using this dual encoding strategy, 5832 (183)-individual peptides/peptoids can be encoded with 3 holes and 18 Raman label compounds. In addition, the method can be easily extended to encode more than one hundred billion ligands by expanding to 9 patterns with 3 holes in binary code. After pentapeptoids were encoded with DM-IDs during solid phase synthesis, the peptoid’s affinity towards streptavidin is successfully evaluated, and the on-bead peptoid sequence is determined by the graphical patterns and the SERS signatures of the DM-IDs. We believe that this encoding method using DM-IDs is a promising tool to construct one-bead-one-compound (OBOC) combinatorial libraries for drug discovery.

Graphical and SERS dual-modal identifier for encoding OBOC library

We propose physical unclonable function (PUF) operations using ferroelectric tunnel junctions (FTJs) and verify the effects of their dimension scaling on the PUF. First, device-to-device variation and within-device reproducibility were measured from the FTJs with various dimensions, which were to be embedded to $4\times 4$ FTJ cross-point array. Then, to obtain inter- and intra-chip fractional hamming distances (HDs), intra-chip reproducibility and inter-chip uniqueness were extracted from the FTJ array simulations. As a result, it is revealed that the more stable PUF operations are achievable in the cross-point array with scaled FTJs since inter-device variation is deteriorated much more seriously by the variation of domain number in the ferroelectric layer than intra-device variation.

Physical Unclonable Functions Using Ferroelectric Tunnel Junctions

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

/pdf/low-latency-spiking-neural-networks-using-pre-charged-5zcya5eg1g.pdf

Min-Hye Oh

Papers

Sensitivity Analysis Based on Neural Network for Optimizing Device Characteristics

Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks.

Graphical and SERS dual-modal identifier for encoding OBOC library

Physical Unclonable Functions Using Ferroelectric Tunnel Junctions

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.