Min Yang

Bio: Min Yang is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 36, co-authored 123 publications receiving 5727 citations. Previous affiliations of Min Yang include Fudan University & GlobalFoundries.

Silicon Device Scaling to the Sub-10-nm Regime

Abstract: In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

Abstract: A six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer. Scattering assisted by phonons and surface roughness has been accounted for, also comparing a full anisotropic model to an approximated isotropic treatment of the matrix elements. Satisfactory qualitative (and in several cases also quantitative) agreement is found between experimental data and theoretical results for the density and temperature dependence of the mobility for (001) surfaces, as well as for the dependence of the mobility on surface orientation [for the (011) and (111) surfaces]. Both compressive and tensile strain are found to enhance the mobility, while confinement effects result in a reduced hole mobility for a Si thickness ranging from 30 to 3 nm.

Benchmarking Organic Micropollutants in Wastewater, Recycled Water and Drinking Water with In Vitro Bioassays

Abstract: Thousands of organic micropollutants and their transformation products occur in water Although often present at low concentrations, individual compounds contribute to mixture effects Cell-based bioassays that target health-relevant biological endpoints may therefore complement chemical analysis for water quality assessment The objective of this study was to evaluate cell-based bioassays for their suitability to benchmark water quality and to assess efficacy of water treatment processes The selected bioassays cover relevant steps in the toxicity pathways including induction of xenobiotic metabolism, specific and reactive modes of toxic action, activation of adaptive stress response pathways and system responses Twenty laboratories applied 103 unique in vitro bioassays to a common set of 10 water samples collected in Australia, including wastewater treatment plant effluent, two types of recycled water (reverse osmosis and ozonation/activated carbon filtration), stormwater, surface water, and drinking water Sixty-five bioassays (63%) showed positive results in at least one sample, typically in wastewater treatment plant effluent, and only five (5%) were positive in the control (ultrapure water) Each water type had a characteristic bioanalytical profile with particular groups of toxicity pathways either consistently responsive or not responsive across test systems The most responsive health-relevant endpoints were related to xenobiotic metabolism (pregnane X and aryl hydrocarbon receptors), hormone-mediated modes of action (mainly related to the estrogen, glucocorticoid, and antiandrogen activities), reactive modes of action (genotoxicity) and adaptive stress response pathway (oxidative stress response) This study has demonstrated that selected cell-based bioassays are suitable to benchmark water quality and it is recommended to use a purpose-tailored panel of bioassays for routine monitoring

Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Abstract: We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.

High performance CMOS fabricated on hybrid substrate with different crystal orientations

Abstract: A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy CMOS devices with physical gate oxide thickness of 12 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm

Architecting phase change memory as a scalable dram alternative

Abstract: Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

Abstract: 1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Phase Change Memory

Abstract: In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Abstract: Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.