Threshold Switching of Ag or Cu in Dielectrics: Materials, Mechanism, and Applications

Over the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0883769400003201

Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials

In current work, the effect of the growth cycles of atomic-layer-deposition (ALD) derived ultrathin Al2O3 interfacial passivation layer on the interface chemistry and electrical properties of MOS capacitors based on sputtering-derived HfTiO as gate dielectric on InGaAs substrate. Significant suppression of formation of Ga–O and As–O bond from InGaAs surface after deposition of ALD Al2O3 with growth cycles of 20 has been achieved. X-ray photoelectron spectroscopy (XPS) measurements have confirmed that suppressing the formation of interfacial layer at HfTiO/InGaAs interface can be achieved by introducing the Al2O3 interface passivation layer. Meanwhile, increased conduction band offset and reduced valence band offset have been observed for HfTiO/Al2O3/InGaAs gate stack. Electrical measurements of MOS capacitor with HfTiO/Al2O3/InGaAs gate stacks with dielectric thickness of ∼4 nm indicate improved electrical performance. A low interface-state density of (∼1.9) × 1012 eV–1 cm–2 with low frequency dispersion ...

Modulating the Interface Quality and Electrical Properties of HfTiO/InGaAs Gate Stack by Atomic-Layer-Deposition-Derived Al2O3 Passivation Layer

Lacking a suitable gate insulator, practical GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) have remained all but a dream for more than four decades. The physics and chemistry of III–V compound semiconductor surfaces or interfaces are problems so complex that our understanding is still limited even after enormous research efforts. Most research is focused on surface pretreatments, oxide formation, and dielectric materials; less attention is paid to the III–V substrate itself. The purpose of this article is to show that device physics more related to III–V substrates is as important as surface chemistry for realizing high-performance III–V MOSFETs. The history and present status of III–V MOSFET research are briefly reviewed. A model based on the charge neutrality level is proposed to explain all experimental work he performed on III–V MOSFETs using ex situ atomic-layer-deposited high-k dielectrics. This model can also explain all reported experimental observations on III–V MOSFETs using ...

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Main determinants for III–V metal-oxide-semiconductor field-effect transistors (invited)

Recently, significant progress has been made on GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using atomic-layer deposition (ALD)-grown Al2O3 as gate dielectric. We show here that further improvement can be achieved by inserting a thin In0.2Ga0.8As layer as part of the channel between Al2O3 and GaAs channel. A 1-μm-gate-length, depletion-mode, n-channel In0.2Ga0.8As/GaAs MOSFET with an Al2O3 gate oxide of 160 A shows a gate leakage current density less than 10−4 A/cm2, a maximum transconductance ∼105 mS/mm, and a strong accumulation current at Vgs>0 in addition to buried-channel conduction. Together with longer gate-length devices, we deduce electron accumulation surface mobility for In0.2Ga0.8As as high as 660 cm2/V s at Al2O3/In0.2Ga0.8As interface.

Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition

The authors demonstrate a passivation technique for GaAs substrate by employing an aluminum oxynitride (AlON) interfacial passivation layer X-ray photoelectron spectroscopy and transmission electron microscopy results show that the AlON interfacial passivation layer effectively suppresses the formation of Ga or As oxide during the gate dielectric deposition process This enabled the fabrication of high quality GaAs n-channel metal-oxide-semiconductor capacitors with HfO2 gate dielectric and TaN metal gate electrode The metal gate/high-k gate dielectric stack on GaAs demonstrated an equivalent SiO2 thickness of 22nm and low leakage current density of 427×10−4A∕cm2 at a gate bias equal to Vfb−1V Excellent capacitance-voltage characteristics with low frequency dispersion (∼4%) were also obtained

Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenide

In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane treatment), alternative gold-free palladium-germanium (PdGe) source and drain (S/D) ohmic contacts, and silicon plus phosphorus coimplanted S/D regions. With the novel in situ surface passivation, excellent capacitance-voltage characteristics with low-frequency dispersion and small stretch-out can be achieved, indicating low interface state density. This surface-channel GaAs device exhibits excellent transistor output characteristics with a high drain current on/off ratio of 105 and a high peak electron mobility of 1230 cm2/V ldr s. In addition, gold contamination concerning CMOS technology can be alleviated with the successful integration of low-resistance PdGe ohmic contacts.

In Situ Surface Passivation and CMOS-Compatible Palladium–Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs

Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon $(\hbox{Si}_{1 - y}\hbox{C}_{y})$ Source and Drain Stressors With High Carbon Content

We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.

A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack

Ming Zhu

Papers

Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenide

In Situ Surface Passivation and CMOS-Compatible Palladium–Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon $(\hbox{Si}_{1 - y}\hbox{C}_{y})$ Source and Drain Stressors With High Carbon Content

A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack