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Minjoo L. Lee

Bio: Minjoo L. Lee is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Electron mobility & Strained silicon. The author has an hindex of 21, co-authored 49 publications receiving 2638 citations.

Papers published on a yearly basis

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Journal ArticleDOI
TL;DR: A review of the history and current progress in highmobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field effect transistors (MOSFETs) can be found in this article.
Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

918 citations

Journal ArticleDOI
TL;DR: In this article, a strained Ge channel p-type metal-oxide-semiconductor field effect transistors (p-MOSFETs) were fabricated on Si0.3Ge0.7 virtual substrates.
Abstract: We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

282 citations

Journal ArticleDOI
TL;DR: In this article, the authors achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates.
Abstract: We have achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field-effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. To further investigate hole transport in these dual channel structures, we study the effects of strain, alloy scattering, and layer thickness on hole mobility enhancements in MOSFETs based upon these layers. We show that significant performance boosts can be obtained despite the effects of alloy scattering and that the best hole mobility enhancements are obtained for structures with thin Si surface layers.

173 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition, and showed that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices.
Abstract: Strained Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si0.7Ge0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then ...

165 citations

Journal ArticleDOI
TL;DR: In this paper, the growth of tensile-strained Ge on relaxed InxGa1−xAs epitaxial templates by metal-organic chemical vapor deposition was investigated.
Abstract: Highly tensile-strained Ge thin films and quantum dots have the potential to be implemented for high mobility metal-oxide-semiconductor field-effect transistor channels and long-wavelength optoelectronic devices. To obtain large tensile strain, Ge has to be epitaxially grown on a material with a larger lattice constant. We report on the growth of tensile-strained Ge on relaxed InxGa1−xAs epitaxial templates by metal-organic chemical vapor deposition. To investigate the methods to achieve high quality Ge epitaxy on III–V semiconductor surfaces, we studied Ge growth on GaAs with variable surface stoichiometry by employing different surface preparation processes. Surfaces with high Ga-to-As ratio are found to be necessary to initiate defect-free Ge epitaxy on GaAs. With proper surface preparation, tensile-strained Ge was grown on relaxed InxGa1−xAs with a range of In content. Low growth temperatures between 350 and 500 °C suppress misfit dislocation formation and strain relaxation. Planar Ge thin films with ...

119 citations


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Journal ArticleDOI
22 Dec 2011-Nature
TL;DR: A solution-processing technique in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules should aid the development of high-performance, low-cost organic semiconducting devices.
Abstract: A solution-processing method known as solution shearing is used to introduce lattice strain to organic semiconductors, thus improving charge carrier mobility. Solution-processed organic semiconductors show great promise for application in cheap and flexible electronic devices, but generally suffer from greatly reduced electronic performance — most notably charge-carrier mobilities — compared with their inorganic counterparts. Borrowing a trick from the inorganic semiconductor community, Giri et al. show how the introduction of strain into an organic semiconductor, through a simple solution-processing technique, modifies the molecular packing within the material and hence its electronic performance. For one material studied, the preparation of a strained structure is shown to more than double the charge-carrier mobility. Circuits based on organic semiconductors are being actively explored for flexible, transparent and low-cost electronic applications1,2,3,4,5. But to realize such applications, the charge carrier mobilities of solution-processed organic semiconductors must be improved. For inorganic semiconductors, a general method of increasing charge carrier mobility is to introduce strain within the crystal lattice6. Here we describe a solution-processing technique for organic semiconductors in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules. For organic semiconductors, the spacing between cofacially stacked, conjugated backbones (the π–π stacking distance) greatly influences electron orbital overlap and therefore mobility7. Using our method to incrementally introduce lattice strain, we alter the π–π stacking distance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) from 3.33 A to 3.08 A. We believe that 3.08 A is the shortest π–π stacking distance that has been achieved in an organic semiconductor crystal lattice (although a π–π distance of 3.04 A has been achieved through intramolecular bonding8,9,10). The positive charge carrier (hole) mobility in TIPS-pentacene transistors increased from 0.8 cm2 V−1 s−1 for unstrained films to a high mobility of 4.6 cm2 V−1 s−1 for a strained film. Using solution processing to modify molecular packing through lattice strain should aid the development of high-performance, low-cost organic semiconducting devices.

965 citations

Journal ArticleDOI
TL;DR: A review of the history and current progress in highmobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field effect transistors (MOSFETs) can be found in this article.
Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

918 citations

Journal ArticleDOI
TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.
Abstract: Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

740 citations

Journal ArticleDOI
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

728 citations