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Minseo Kim

Bio: Minseo Kim is an academic researcher from KAIST. The author has contributed to research in topics: Electrical impedance tomography & Electrical impedance. The author has an hindex of 11, co-authored 27 publications receiving 343 citations.

Papers
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Journal ArticleDOI
Minseo Kim1, Unsoo Ha1, Kyuho Jason Lee1, Yongsu Lee1, Hoi-Jun Yoo1 
TL;DR: An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed, which successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure- of-merit of 0.3 pJ/bit.
Abstract: An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm2 in 0.18- $\mu \text{m}$ CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit.

69 citations

Journal ArticleDOI
Hyunwoo Cho1, Hyunki Kim1, Minseo Kim1, Jaeeun Jang1, Yongsu Lee1, Kyuho Jason Lee1, Joonsung Bae1, Hoi-Jun Yoo1 
TL;DR: The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves >60dB interference rejection with 100 kb/s data rate and 42.5μW power consumption under the 0.8 V supply.
Abstract: A low-energy 40/160 MHz dual-band full duplex body channel communication (BCC) transceiver and a 13.56 MHz R-C oscillator-based super-regenerative transceiver are integrated in 65 nm CMOS mixed mode process for both entertainment and healthcare applications. The on-chip R-C duplexer uses notch filters for full duplex communication with 40 Mb/s data rate and combined dual-band operation shows 80 Mb/s data rate with half duplex communication. 40 MHz sine wave and 160 MHz rectangular wave are adopted for modulation in the dual-band transmitter with 30 dB SNR improvement, and shared-loop BPSK receiver reduces the power consumption by 25%. The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves ${>}60\,\text{dB}$ interference rejection with 100 kb/s data rate and $42.5\,\upmu\text{W}$ power consumption under the 0.8 V supply.

56 citations

Journal ArticleDOI
Unsoo Ha1, Jae Hyuk Lee1, Minseo Kim1, Taehwan Roh, Sangsik Choi2, Hoi-Jun Yoo1 
TL;DR: A multimodal head-patch system that simultaneously measures EEG and near-infrared spectroscopy (NIRS) on the frontal lobe is proposed and can show the clinically important transition from the awake to deep state, but BIS cannot detect the transition in a clinical trial.
Abstract: In surgical operation environments, anesthesia enables doctors to safe and accurate medical process with minimized movement and pain of patients. In general anesthesia, non-invasive and reliable monitoring of anesthesia depth is required because it is directly related to patient’s life. However, the current anesthesia depth monitoring approach, bispectral index (BIS), uses only electroencephalography (EEG) from the frontal lobe, and it shows critical limitations in the monitoring of anesthesia depth such as signal distortion due to electrocautery, electromyography (EMG) and dried gel, and false response to the special types of anesthetic drugs. In this paper, a multimodal head-patch system that simultaneously measures EEG and near-infrared spectroscopy (NIRS) on the frontal lobe is proposed. For EEG monitoring, mixed-mode dc-servo loop is proposed to cancel out the ±300-mV electrode-dc offset for dried gel condition with 3.59 noise-efficiency factor. To compensate the electromagnetic noises (EMG and electrocautery) in the system level, NIRS signal is measured. Logarithmic transimpedance amplifier (TIA) and closed-loop controlled (CLC) NIRS current driver are proposed. Logarithmic TIA can reject ambient light up to 10 nA to achieve a 60-dB dynamic range. According to the comparator output, CLC NIRS driver duty cycle can be adjusted from 0.625 m to 50 ms adaptively. The 16-mm2 system-on-chip is fabricated in 65-nm CMOS. It dissipates 25.2-mW peak power. With the combined signals, it can show the clinically important transition from the awake to deep state, but BIS cannot detect the transition in a clinical trial.

50 citations

Proceedings ArticleDOI
Hyunwoo Cho1, Hyunki Kim1, Minseo Kim1, Jaeeun Jang1, Joonsung Bae1, Hoi-Jun Yoo1 
19 Mar 2015
TL;DR: Body channel communication, which uses the human body as the communication channel, has demonstrated better human-friendly interface and energy-efficient performance compared with air channel communication but did not support full duplex communication so that the user interaction with wearable devices was not possible in live video streaming or real-time VR game applications.
Abstract: Recently, smart phones or head-mounted displays enables high definition (HD) video streaming and image data to be shared with friends while wearable smart sensors continuously monitor and send user's physiological information to a smart watch. Body channel communication (BCC), which uses the human body as the communication channel [1], has demonstrated better human-friendly interface and energy-efficient performance compared with air channel communication. However, most of the previous BCC research used only the frequency band below 100MHz and were only focused on either low data rate (<10Mb/s) healthcare applications [2-5] or high data rate (60Mb/s) multimedia data transfer [6]. Its available channel bandwidth was limited < 100MHz and the interference from FM radio due to body antenna effect had a significant effect on its performance. Moreover, [6] did not support full duplex communication so that the user interaction with wearable devices was not possible in live video streaming or real-time VR game applications.

48 citations

Journal ArticleDOI
TL;DR: A wearable electrical impedance tomography (EIT) system is proposed for the portable real-time 3-D lung ventilation monitoring, and EIT images are reconstructed with 90% of accuracy, and up to 10 frames/s real- Time Difference lung images are successfully displayed.
Abstract: A wearable electrical impedance tomography (EIT) system is proposed for the portable real-time 3-D lung ventilation monitoring. It consists of two types of SoCs, active electrode (AE)-SoC and Hub-SoC, mounted on wearable belts. The 48-channel AE-SoCs are integrated on flexible printed circuit board belt, and Hub-SoC is integrated in the hub module which performs data gathering and wireless communication between an external imaging device. To get high accuracy under the variation of conductivity, the dual-mode current stimulator provides the optimal frequency for time difference-EIT and frequency difference-EIT with simultaneous 4 k–128 kHz impedance sensing. A wide dynamic range instruments amplifier is proposed to provide 94 dB of wide dynamic range impedance sensing. In addition, the 48-channel AE system with the dedicated communication and calibration is implemented to achieve 1.4- $\text{m}\Omega $ sensitivity of impedance difference in the in vivo environment. The AE-/Hub-SoCs occupy 3.2 and 1.3 mm2 in 65-nm CMOS technology and consume $124~\mu \text{W}$ and 1.1 mW with 1.2 V supply, respectively. As a result, EIT images are reconstructed with 90% of accuracy, and up to 10 frames/s real-time 3-D lung images are successfully displayed.

43 citations


Cited by
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Journal ArticleDOI
TL;DR: A machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine- learning model, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns.
Abstract: This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model. Peripheral circuits implement mixed-signal weak classifiers via columns of the SRAM, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns. A prototype 128 $\times $ 128 SRAM array, implemented in a 130-nm CMOS process, demonstrates ten-way classification of MNIST images (using image-pixel features downsampled from 28 $\times $ 28 = 784 to 9 $\times $ 9 = 81, which yields a baseline accuracy of 90%). In SRAM mode (bit-cell read/write), the prototype operates up to 300 MHz, and in classify mode, it operates at 50 MHz, generating a classification every cycle. With accuracy equivalent to a discrete SRAM/digital-MAC system, the system achieves ten-way classification at an energy of 630 pJ per decision, 113 times lower than a discrete system with standard training algorithm and 13 times lower than a discrete system with the proposed training algorithm.

376 citations

Proceedings ArticleDOI
11 Jul 2016
TL;DR: A HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a core area of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V is presented.
Abstract: Convolutional Neural Networks (CNNs) have revolutionized the world of image classification over the last few years, pushing the computer vision close beyond human accuracy. The required computational effort of CNNs today requires power-hungry parallel processors and GP-GPUs. Recent efforts in designing CNN Application-Specific Integrated Circuits (ASICs) and accelerators for System-On-Chip (SoC) integration have achieved very promising results. Unfortunately, even these highly optimized engines are still above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. On the algorithmic side, highly competitive classification accuracy canbe achieved by properly training CNNs with binary weights. This novel algorithm approach brings major optimization opportunities in the arithmetic core by removing the need for the expensive multiplications as well as in the weight storage and I/O costs. In this work, we present a HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a corearea of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V. Our accelerator outperforms state-of-the-art performance in terms of ASIC energy efficiency as well as area efficiency with 61.2 TOp/s/W and 1135 GOp/s/MGE, respectively.

199 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present an accelerator optimized for binary-weight CNNs that achieves 1.5 TOp/s at 1.2 V on a core area of only 1.33 million gate equivalent (MGE) or 1.6 V.
Abstract: Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today’s CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have reduced energy consumption significantly. Unfortunately, even these highly optimized devices are above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. This prevents the adoption of CNNs in future ultralow power Internet of Things end-nodes for near-sensor analytics. Recent algorithmic and theoretical advancements enable competitive classification accuracy even when limiting CNNs to binary (+1/−1) weights during training. These new findings bring major optimization opportunities in the arithmetic core by removing the need for expensive multiplications, as well as reducing I/O bandwidth and storage. In this paper, we present an accelerator optimized for binary-weight CNNs that achieves 1.5 TOp/s at 1.2 V on a core area of only 1.33 million gate equivalent (MGE) or 1.9 mm 2 and with a power dissipation of 895 $\mu$ W in UMC 65-nm technology at 0.6 V. Our accelerator significantly outperforms the state-of-the-art in terms of energy and area efficiency achieving 61.2 TOp/s/W@0.6 V and 1.1 TOp/s/MGE@1.2 V, respectively.

198 citations

Journal ArticleDOI
Jinouk Song1, Hyeonwoo Lee1, Eun Gyo Jeong1, Kyung Cheol Choi1, Seunghyup Yoo1 
TL;DR: It is indicated that EQE close to 58% and 80% can be within reach without and with additional light extraction structures, respectively, with an optimal combination of cavity engineering, low-index transport layers, and horizontal dipole orientation.
Abstract: Organic light-emitting diodes (OLEDs) are established as a mainstream light source for display applications and can now be found in a plethora of consumer electronic devices used daily. This success can be attributed to the rich luminescent properties of organic materials, but efficiency enhancement made over the last few decades has also played a significant role in making OLEDs a practically viable technology. This report summarizes the efforts made so far to improve the external quantum efficiency (EQE) of OLEDs and discusses what should further be done to push toward the ultimate efficiency that can be offered by OLEDs. The study indicates that EQE close to 58% and 80% can be within reach without and with additional light extraction structures, respectively, with an optimal combination of cavity engineering, low-index transport layers, and horizontal dipole orientation. In addition, recent endeavors to identify possible applications of OLEDs beyond displays are presented with emphasis on their potential in wearable healthcare, such as OLED-based pulse oximetry as well as phototherapeutic applications based on body-attachable flexible OLED patches. OLEDs with fabric-like form factors and washable encapsulation strategies are also introduced as technologies essential to the success of OLED-based wearable electronics.

189 citations

Journal ArticleDOI
TL;DR: Thinker is an energy efficient reconfigurable hybrid-NN processor fabricated in 65-nm technology designed to exploit data reuse and guarantee parallel data access, which improves computing throughput and energy efficiency.
Abstract: Hybrid neural networks (hybrid-NNs) have been widely used and brought new challenges to NN processors. Thinker is an energy efficient reconfigurable hybrid-NN processor fabricated in 65-nm technology. To achieve high energy efficiency, three optimization techniques are proposed. First, each processing element (PE) supports bit-width adaptive computing to meet various bit-widths of neural layers, which raises computing throughput by 91% and improves energy efficiency by $1.93 \times $ on average. Second, PE array supports on-demand array partitioning and reconfiguration for processing different NNs in parallel, which results in 13.7% improvement of PE utilization and improves energy efficiency by $1.11 \times $ . Third, a fused data pattern-based multi-bank memory system is designed to exploit data reuse and guarantee parallel data access, which improves computing throughput and energy efficiency by $1.11 \times $ and $1.17 \times $ , respectively. Measurement results show that this processor achieves 5.09-TOPS/W energy efficiency at most.

185 citations