Minzhi Wang

Bio: Minzhi Wang is an academic researcher. The author has contributed to research in topics: Low voltage. The author has an hindex of 1, co-authored 1 publications receiving 29 citations.

A High-Speed Deep-Trench MOSFET With a Self-Biased Split Gate

Abstract: A split-gate deep-trench MOSFET (DT-MOS) with its split gate self-biased to an integrated low voltage supply is proposed. Due to the split gate being biased to an approximately constant voltage, this structure has a smaller amount of gate-to-drain charge Qgd without increase in the specific on-resistance Ron, compared with the conventional DT-MOS. Numerical simulation results show that the figure of merit (FOM = Qgd ·Ron) is largely reduced, compared with that of the conventional DT-MOS.

Adaptive dv/dt and di/dt control for isolated gate power devices

Abstract: This paper describes an adaptive gate control technique and a driver concept for isolated gate power devices. The proposed technique modulates the gate current of the power devices to control dv/dt and di/dt during a switching transition. It uses different time intervals, which are adjusted successively. Delays of the driver and the control section are compensated and therefore the proposed technique is applicable to control fast switching transients. To detect the di/dt during switching, a feedback path is implemented using parasitic inductances in the power section of the converter. By application of this method, we achieved the following properties: low propagation delays, reduced voltage overshoots, improved EMI and reduced switching power losses. The proposed method is applicable to converters with half-bridge, full-bridge and three-phase bridge configuration.

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

Abstract: In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

A Split Triple-Gate Power LDMOS With Improved Static-State and Switching Performance

Abstract: A novel split triple-gate (STG) LDMOS is proposed to improve static-state and switching performances. The proposed structure features a triple-gate and split gates (SGs). The triple-gate consists of planar part and trench part, and the SGs are embedded into the drift region and isolated with slanted oxide. The triple-gate enlarges the channel width. Furthermore, the trench part of triple-gate and trench drain–source contributes to a uniform on-state current density distribution from the surface to the bottom of the drift region, resulting in a high average current density. Consequently, the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ) and the transconductance are improved. In the off-state, the SGs act as a slanted field plate to not only modulate the electric field distribution, but also assist in depleting the drift region to increase the optimal doping concentration, which further decreases the ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ and maintains a high BV. Moreover, the SG is introduced to reduce the gate–drain capacitance and switching power dissipation. Compared with the triple-gate LDMOS (TG LDMOS), the STG LDMOS not only reduces the ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ by 66%, but also decreases the gate–drain charge by 41%.

Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa

Abstract: An optimized split-gate-enhanced UMOSFET (SGE-UMOS) layout design is proposed, and its mechanism is investigated by 2-D and 3-D simulations. The layout features trench surrounding mesa (TSM): First, it optimizes the distribution of electric field density in the outer active mesa, reduces the electric-field crowding effect, and improves the breakdown voltage of the SGE-UMOS device. Second, it is unnecessary to design the layout corner with a large diameter in the termination region for the TSM structure as the conventional mesa surrounding trench (MST) structure, which is more efficient in terms of silicon usage. Rsp.on is reduced when compared with the MST structure within the same rectangular chip area. The BV of SGE-UMOS is increased from 72 to 115 V, and Rsp.on is reduced by approximately 3.5% as compared with the MST structure, due to the application of the TSM. Finally, it needs five masks in the process, and the trenches in active and termination regions are formed with the same processing steps; hence, the manufacturing process is simplified, and the cost is reduced as well.

High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels

Abstract: This paper presents an optimized split-gate-enhanced trench MOSFET with dual channels (DSGE-UMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance ( ${R}_{ {\mathrm{\scriptscriptstyle ON}}\text {-sp}}$ ) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot.