This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Area efficient modified vedic multiplier

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

The modern systems are denser and faster. But these systems consume more power. The variants of power dissipation are dynamic power, leakage power, short circuit power and static power dissipation. Adders, Shifters and Multipliers are the essential building blocks of any Digital Signal Processor (DSP) architecture. Hence design of these building blocks to dissipate less power is of utmost importance in digital system design. In order to reduce this power dissipation, there are many low power approaches such as Multi-Vth, reducing the voltage swing, clock gating, use of reversible logic gates etc. The main advantage of designing circuit using reversible logic gates is that the designed circuits will be compatible with the available resources. Reversible Logic gates are that logic gates which have the same number of inputs and outputs and all the outputs are unique for a given input combination. These gates are used to reduce the power dissipation due to loss of information bits. The functional verification of the conventional and reversible Kogge-stone Adder, Vedic Multiplier and Barrel Shifter is performed using Verilog in Xilinx ISE and the power, delay and area of the Kogge-stone Adder, Vedic Multiplier and Barrel Shifter are computed using Cadence RTL compiler software in 90 nm technology. The proposed reversible Vedic Multiplier consumed 0.621 % less power than the conventional Vedic Multiplier. The power dissipation of reversible Barrel Shifter is found to be 26.49 % less than conventional Barrel Shifter.

Design of low power barrel shifter and vedic multiplier with kogge-stone adder using reversible logic gates

Multiplication is basic function in arithmetic operations. Multiplication based operations such as multiply and Accumulate unit (MAC), convolution, Fast Fourier Transform (FFT), filtering are widely used in signal processing applications. As, multiplication dominates the execution time of DSP systems, there is need to develop high speed multipliers. Ancient Vedic mathematics facilitates the solution to some extent. In this paper, concept of Urdhwa-Tiryagbhyam is used i.e., vertically and crosswise multiplication to implement 16×16 Bit Vedic multiplier and optimization is achieved by using carry save adders. Comparing with previous architectures, proposed architecture achieves 33.26% reduction in combinational path delay. The Vedic multiplier proposed is implemented in VHDL whereas synthesized and simulated using Xilinx ISE Design Suite 14.5.

Design and optimization of 16×16 Bit multiplier using Vedic mathematics

This article proposes a new hardware implementation for a Reconfigurable Neural Network for systems in which the topology needs flexibility. The used architecture is a MultiLayer Perceptron, where the entry of a layer depends on the output of the previous layer. The approach allows flexibility in the number of network inputs, neurons, layers and in the activation function executed by neurons. Despite having been developed for FPGAs, the implemented circuit allows its implementation in ASIC, since it does not use proprietary internal blocks of the FPGA. By submitting the network to approximation tests, its operation and flexibility has been checked and validated.

Implementation of a reconfigurable neural network in FPGA

Today's technology has raised demand for Fast and real time signal processing operation. Multiplication is one of the most important arithmetic operations. In this paper, we have proposed design of vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE. This design takes lesser time for operation than currently available multipliers .It encompasses wide era of image processing and digital signal processing in much efficient way with increase in speed and thus leading to higher performance rating

Miss. Shilpa Jadhav

Papers

Design And Implementation Of 8-bit Vedic Multiplier