Some embodiments described herein include a system that collects and learns reference side-channel normal activity, process it to reveal key features, compares subsequent collected data and processed data for anomalous behavior, and reports such behavior to a management center where this information is displayed and predefine actions can be executed when anomalous behavior is observed. In some instances, a physical side channel (e.g. and indirect measure of program execution such as power consumption or electromagnetic emissions and other physical signals) can be used to assess the execution status in a processor or digital circuit using an external monitor and detect, with extreme accuracy, when an unauthorized execution has managed to disrupt the normal operation of a target system (e.g., a computer system, etc.).

Systems, methods, and apparatuses for intrusion detection and analytics using power characteristics such as side-channel information collection

A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Temperature variation compensation

A motor control apparatus includes a by-wire control circuit for sequentially switching an energized phase of a motor. The by-wire control circuit pre-stores a first table defining an energized phase address corresponding to each address and a second table defining an energized phase corresponding to each energized phase address. When receiving a drive permission code from a second control circuit, the by-wire control circuit switches the energized phase in a correct order of driving the motor, by calculating an address for access to the first table based on the drive permission code, calculating an energized phase address corresponding to the address by referring to the first table, and determining the energized phase corresponding to the energized phase address by referring to the second table.

Motor control apparatus

Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.

Power management device and system-on-chip including the same

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Memory cell array latchup prevention

A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

Method and apparatus for limiting access to an integrated circuit (IC)

A voltage regulation system includes a voltage regulator configured to output a control signal indicating whether a voltage based on output of the voltage regulator is lower than a specified value. A charge pump is configured to output a voltage and a charging current. A pump monitor is configured to receive the control signal and the output voltage of the charge pump, and activate the charge pump when the control signal indicates the voltage based on output of the voltage regulator is lower than a specified value and the output voltage of the charge pump is lower than a threshold value.

Charge pump LDO with secondary sensing for low power need based refresh

A device includes a comparator, and a selection circuit coupled to the inputs of the comparator. The selection circuit receives reference voltages and a variable voltage. In a normal operation mode, the selection circuit provides the variable voltage and a selected reference voltage to the comparator and the comparator provides an indication based on the variable voltage. In a test mode, the selection circuit provides a first selected reference voltage and a second selected reference voltage to the comparator for determining a switching offset voltage of the comparator.

Circuit and method for determining comparator offsets of electronic devices

A voltage regulator has an output driver current mirror circuit and one or more control circuits The output driver current mirror circuit includes an output driver transistor, a tunable resistance circuit, and a diode-connected transistor The output driver transistor has one current electrode coupled to a supply voltage and another current electrode coupled to an output terminal for providing the output voltage of the voltage regulator The tunable resistance circuit has one terminal coupled to a control electrode of the output driver transistor, and another terminal coupled to a current electrode of the diode-connected transistor The one or more control circuits includes a comparator for controlling a current provided to the output driver current mirror in response to a feedback signal from the output terminal

Tunable voltage regulator circuit

An IC provides tracking between multiple regulated voltages. The IC includes, a voltage reference circuit, a voltage multiplier circuit, and first and second voltage regulator circuits. The voltage reference circuit generates a first reference voltage. The first voltage regulator circuit generates, at a first terminal of a first output transistor, a first regulated voltage that is based on the first reference voltage. The voltage multiplier circuit generates a second reference voltage from an equivalent of the first reference voltage. The second voltage regulator circuit generates, at a first terminal of a second output transistor, a second regulated voltage that is based on the second reference voltage. At least one terminal of the second output transistor is capacitively coupled to the first terminal of the first output transistor.

Miten H. Nagda

Papers

Method and apparatus for limiting access to an integrated circuit (IC)

Charge pump LDO with secondary sensing for low power need based refresh

Circuit and method for determining comparator offsets of electronic devices

Tunable voltage regulator circuit

Method and integrated circuit that provides tracking between multiple regulated voltages