Mohammad Hossein Moaiyeri

Bio: Mohammad Hossein Moaiyeri is an academic researcher from Shahid Beheshti University. The author has contributed to research in topics: Adder & Carbon nanotube field-effect transistor. The author has an hindex of 27, co-authored 139 publications receiving 2302 citations.

Design of energy-efficient and robust ternary circuits for nanotechnology

Abstract: Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Abstract: Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Abstract: This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

A new quantum-dot cellular automata full-adder

Abstract: Physical limitations for CMOS technology have provided the way for manufacturing the quantum cellular automata technology-based hardware elements at Nano level. From the purpose of very high speed, area and low power consumption, this Nanotechnology has been taken into consideration. Improving their structures will lead promoting the system performance completely, because the Full adders are assumed as major and primary component of computational processors. In current study, the new layout of all single bit full adders in the quantum cellular automata's technology is introduced. In comparison with existing schemes, the suggested circuit has fewer cells and smaller area.

Super-Resolution Imaging

Abstract: This book serves as an introduction to the flourishing field of super-resolution imaging. It is a compiled volume, with different authors for each of its 14 chapters. While not having a strong outline or textbook format, the chapters group into several sections.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Abstract: In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Design of energy-efficient and robust ternary circuits for nanotechnology

Abstract: Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.