Mona Safi-Harb

Bio: Mona Safi-Harb is an academic researcher from McGill University. The author has contributed to research in topics: CMOS & Undersampling. The author has an hindex of 6, co-authored 14 publications receiving 116 citations. Previous affiliations of Mona Safi-Harb include École Polytechnique de Montréal & Montreal Neurological Institute and Hospital.

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

Abstract: This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.

70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS

Abstract: This paper examines a time-base measurement system for on-chip digitization. Undersampling, combined with single-path time-domain amplification and processing, is used to perform the embedded measurement in a time-efficient manner. The proposed system relies on simple circuit components while performing high-speed measurements. Additionally, ease of calibration with minimal silicon area overhead renders the system attractive from a design-for-test perspective. The circuit was implemented in a 0.18-mum standard digital CMOS process using a single 1.8-V supply. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using the prototype chip. An effective 70-GHz sampling rate is experimentally obtained from the implemented on-chip oscilloscope, with a voltage resolution of 4 mV. The estimated static power dissipation is ~3.5 mW, with a total active area of 0.45 mm2 taken up by the associated test and calibration vehicles.

Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS

Abstract: This paper examines an embedded low-power technique for the single-shot measurement of GHz digital signals. Two circuits will be demonstrated; the first is a rise time measurement core, while the second represents an embedded technique for the characterization of narrow pulses. Both circuits can be seen as general tools to increase the low-end time dynamic range measurements of digital events in CMOS. The circuits rely on a new fast voltage-crossing detector to convert the input information and condition it into same polarity edges, separated by the timing information to be measured. Those edges are then in turn stretched further using time amplification, making them easily detectable with low-resolution time-to-digital converters. Dynamic current generation techniques are used in the front-end detector to greatly reduce the power consumption. The proposed circuits are compact and introduce only a few tens of femtofarads capacitive loading. The circuits were implemented in a standard 0.18-mum CMOS process. Experimental results show the feasibility of the proposed approach. Rise times of 1 ns and pulses as narrow as 78 ps were successfully captured in a single-shot measurement approach, with total power dissipation not exceeding a few milliwatts, in each of the two cases.

An Implantable Seizure-Onset Detector Based on a Dual-Path Single-Window Count-Based Technique for Closed-Loop Applications

Abstract: In this paper, we present a single voltage-window count-based seizure onset detection algorithm and its associated hardware implementation. The proposed algorithm combines the advantages associated with voltage-window count-based and event-based threshold-voltage detections. The result is an algorithm that is more tolerant to noise, dc offsets, baseline energy variations, and seconds-long nonseizure related sharp activities. In addition, only one parameter (one threshold voltage) needs to be optimized per patient, and for that, only one seizure per patient is used for training, making the process of optimizing the patient-specific detector a simple task. The time evaluation period when counting is performed is kept constant across all patients studied, and is fixed at 5 s in this work. A novel dual path digital signal processing unit in the back-end of the detector is included and is shown to decrease the detection latency by 14%. Experimental results on a printed circuit board using commercially available discrete components confirm the correct functionality of the proposed detector. The proposed algorithm achieves 100% sensitivity, 10.7 s average detection delay, and a single false alarm when evaluated on a total of 25 seizures and 24 nonseizure datasets of intracerebral electroencephalographic (icEEG) recordings from five patients from the epilepsy monitoring unit of Notre-Dame Hospital in Montreal. In addition, monolithic integration of the overall system, including bio-amplification and comparison, is also carried out in a TSMC 0.18- $\mu$ m complementary metal–oxide–semiconductor technology. Simulations show that a static power dissipation of 7 $\mu {\rm W}$ , 99% of which is consumed by the front-end bio-amplifier, is achieved, showing the potential of using the proposed seizure detector in a closed-loop brain–prosthesis device interface for seizure control and treatment.

Hemodynamic Response Function (HRF) in Epilepsy Patients with Hippocampal Sclerosis and Focal Cortical Dysplasia

Abstract: Simultaneous recording of electroencephalography and functional magnetic resonance imaging (EEG–fMRI) has recently been applied for mapping the hemodynamic changes related to epileptic activity. The aim of this study is to compare the hemodynamic response function (HRF) to epileptic spikes in patients with focal cortical dysplasia (FCD) and those with hippocampal sclerosis (HS). In EEG–fMRI studies, the HRF represents the temporal evolution of blood oxygenation level-dependent signal changes. Several studies demonstrated that amplitude and latency of the HRF are variable in patients with epilepsy. However, the consistency of HRF parameters with underlying brain pathology is unknown. In this study, we examined 14 patients with FCD and 12 with unilateral HS selected from our EEG–fMRI database and compared the amplitude and latency of the HRF peak. We analyzed (1) HRFs in peak activation clusters, (2) HRFs in peak deactivation clusters, and (3) the maximum absolute responses within the EEG spike field, activation or deactivation. We found that the HRF peak amplitude in deactivation clusters was larger in the HS group than in the FCD when the deactivation occurred in default mode network (DMN) regions. This result suggests that spikes in patients with HS affect the DMN more strongly than those with FCD. However, if we focus on the maximum absolute t-value in the spike field, there is no significant difference between the two groups. The current study indicates that it is not necessary to use different HRF models for EEG–fMRI studies in patients with FCD and HS.

Seizure Suppression Efficacy of Closed-Loop Versus Open-Loop Deep Brain Stimulation in a Rodent Model of Epilepsy

Abstract: We assess and compare the effects of both closed-loop and open-loop neurostimulation of the rat hippocampus by means of a custom low-power programmable therapeutic neurostimulation device on the suppression of spontaneous seizures in a rodent model of epilepsy. Chronic seizures were induced by intraperitoneal kainic acid injection. Two bipolar electrodes were implanted into the CA1 regions of both hippocampi. The electrodes were connected to the custom-built programmable therapeutic neurostimulation device that can trigger an electrical stimulation either in a periodic manner or upon detection of the intracerebral electroencephalographic (icEEE) seizure onset. This device includes a microchip consisting of a 256-channel icEEG recording system and a 64-channel stimulator, and a programmable seizure detector implemented in a field-programmable gate array (FPGA). The neurostimulator was used to evaluate seizure suppression efficacy in ten epileptic rats for a total of 240 subject-days (5760 subject-hours). For this purpose, all rats were randomly divided into two groups: the no-stimulation group and the stimulation group. The no-stimulation group did not receive stimulation. The stimulation group received, first, closed-loop stimulation and, next, open-loop stimulation. The no-stimulation and stimulation groups had a similar seizure frequency baseline, averaging five seizures per day. Closed-loop stimulation reduced seizure frequency by 90% and open-loop stimulation reduced seizure frequency by 17%, both in the stimulation group as compared to the no-stimulation group.

Delta–Sigma A/D Conversion Via Time-Mode Signal Processing

Abstract: In this paper, a signal processing methodology is proposed that performs delta-sigma (DeltaSigma) analog-to-digital (A/D) conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode (TM) signal processing, uses time-difference variables as an intermediate signal between the input voltage and the digital output. The resulting low-cost silicon devices offer very compact, low-power, high-speed, and robust A/D converter (ADC) alternatives. A first-order DeltaSigma ADC is implemented using this methodology. Two ICs were fabricated in a 0.18- mum CMOS technology to demonstrate the feasibility of the TM DeltaSigma ADC approach. The first IC implements a single-ended input design while a differential design was fabricated in the second IC. Experimental results reveal that these devices can achieve 7-9-bit resolutions within 125-400-kHz bandwidths, while occupying areas smaller than 50 mum t50 mum and consuming less than 800 muW.

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Abstract: A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog converter. Measurements with a 55 MHz crystal clock demonstrate a full-scale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequency-domain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps full-scale delay and 0.34% at 19 ps are measured, representing 8–9 bit effective INL-limited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW.

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Abstract: This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision.

A Review of New Time-to-Digital Conversion Techniques

Abstract: Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.