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Mong-Song Liang

Bio: Mong-Song Liang is an academic researcher from TSMC. The author has contributed to research in topics: Gate oxide & Layer (electronics). The author has an hindex of 37, co-authored 276 publications receiving 5527 citations.


Papers
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Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Abstract: A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

292 citations

Proceedings ArticleDOI
01 Jan 2002
TL;DR: In this paper, low leakage and low active power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity.
Abstract: Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 /spl mu/A//spl mu/m and 780 /spl mu/A//spl mu/m with off state leakage currents of 8 nA//spl mu/m and 0.4 nA//spl mu/m for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 /spl mu/A//spl mu/m for N-FET and 550 /spl mu/A//spl mu/m for P-FET at an off current of 1 /spl mu/A//spl mu/m. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections.

216 citations

Patent
21 Jul 2004
TL;DR: In this article, a gate dielectric and an electrode are formed on a substrate and a pair of spacers are formed along opposite sidewalls of the gate electrode and the gate Dielectric.
Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

179 citations

Patent
19 Mar 2010
TL;DR: In this article, a method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen.
Abstract: A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

139 citations

Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this paper, an advanced stress memorization technique (SMT) for device performance enhancement is presented, where a high-tensile nitride capping layer is removed after the poly and S/D activation procedures.
Abstract: An advanced stress memorization technique (SMT) for device performance enhancement is presented A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation Combining the high tensile nitride sealing layer deposition after silicide process it was found to gain additional /spl sim/10% improvement to NMOS The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process which is a promising local strain approach for sub-65nm CMOS application

127 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
TL;DR: In this article, the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects are discussed.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

1,500 citations

Journal ArticleDOI
TL;DR: In this paper, a review of porosity in on-chip wires can be found, with an attempt to give an overview of the classification, the character, and the characteristics of the porosity.
Abstract: The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

1,496 citations

Patent
02 Aug 1998
TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) with a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed.
Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

1,195 citations

01 Jan 1999
TL;DR: Damascene copper electroplating for on-chip interconnections, a process that was conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition as discussed by the authors.
Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

1,006 citations