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Logical Effort Designing Fast Cmos Circuits

Research on noise impact of building environment based on FPGA high-performance algorithm

This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

This paper presents an analysis of jitter due to various deterministic noise sources in a CMOS inverter. The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained from full SPICE based simulations. For the estimation of jitter, EMPSIJ method [1] is used in the paper. The paper also discusses the sensitivity of various noise paths on jitter.

Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter

This paper presents an efficient method for the estimation of jitter due to power supply noise in a chain-of-inverters including the on-chip-interconnects. An analytical noise transfer function from power supply to output is derived based on a small-signal analysis. The estimation of jitter is done using a slope-based semi-analytical approach and the results are compared with the SPICE-based simulations.

Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

This paper presents an analysis and estimation of timing error due to the power supply noise for a five-stage CMOS tapered buffer used in the clock distribution network for the application of successive approximation register (SAR). The complete design is simulated in standard 28 nm CMOS technology with the supply voltage of 0.9 V. The closed-form expressions for time interval error have been derived using the matrix inversion method, considering the impact of deterministic supply noise. The results obtained from a slope-based semianalytical jitter estimation method are compared with the SPICE based simulations. The results show a good agreement with a maximum error of 4 %.

Muhammed Suhail Illikkal

Papers

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network