Munhyeon Kim

Bio: Munhyeon Kim is an academic researcher from Seoul National University. The author has contributed to research in topics: Capacitance & Field-effect transistor. The author has an hindex of 4, co-authored 10 publications receiving 32 citations.

Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs

Abstract: In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective

Abstract: In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.

Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique

Abstract: In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.

Investigation of Sidewall High- k Interfacial Layer Effect in Gate-All-Around Structure

Abstract: In this article, structure optimization of high- ${k}$ interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High- ${k}$ IL can be formed during the high- ${k}$ gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high- ${k}$ IL ( ${T}_{\text {hk}}$ ) with gate length ( ${L}_{\text {G}}$ ), spacer length ( ${L}_{\text {ext}}$ ), and source/drain (S/D) length ( ${L}_{\text {S/D}}$ ), improved electrical performances were obtained. By optimizing ${T}_{\text {hk}}$ with properly adjusted ${L}_{\text {G}}$ , ${L}_{\text {ext}}$ , and ${L}_{\text {S/D}}$ , highly saturated ON-/OFF-current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay ( ${C}_{\text {gg}}$ ) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when ${L}_{\text {ext}}$ shrinks with extending ${T}_{\text {hk}}$ , was also investigated. Finally, the optimized electrical characteristics were obtained when ${T}_{\text {hk}}$ is adjusted with ${L}_{\text {G}}$ and ${L}_{\text {S/D}}$ . The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when ${T}_{\text {hk}}$ is optimized through ${L}_{\text {G}}$ . On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with ${L}_{\text {S/D}}$ , which result in lower static power. Based on this comparison, optimization method and guideline for high- ${k}$ IL was proposed.

Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation

Abstract: We explicate the negative capacitance (NC) effect in MOS structures through TCAD simulation, and find the influence of electric field variation in ferroelectric layer. Furthermore, pre-researched time-dependent NC effect is explained in more detail. For this purpose, the electric field and potential difference in the ferroelectric layer are analyzed based on the measured data of metal-ferroelectric-metal (MFM) capacitors, and then the parameters for the occurrence of the NC effect in the NCFET were analyzed. This establishes the conditions necessary for the successful operation of the NCFET.

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Abstract: Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (ION/IOFF) = ~107 and good ON-OFF performance metric Q = gm/SS = 2.06 × 10−5 S-dec/μm-mV even at 5 nm LG. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of gm by ~10% have been noticed from SiO2 + HfO2 to Si3N4 + HfO2. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like ft, τ, and GBW. The Air single-k spacer shows good performance for RF applications with ft = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at LG = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO2, Si3N4) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications.

Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel

Abstract: We demonstrate a novel ferroelectric-gate field effect transistor with recessed channel (R-FeFET) to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Based on technology computer-aided design (TCAD) simulations including calibrated ferroelectric material (FE) parameters, it is revealed that the polarization is enhanced by the larger electric field (e-field) across the FE compared to a conventional planar FeFET, resulting in the wider MW and the faster program/erase speed. Moreover, the endurance/retention of the R-FeFET is expected to be improved as the e-field across the SiO2 interlayer is significantly reduced.