Myung-Chul Kim

Bio: Myung-Chul Kim is an academic researcher from IBM. The author has contributed to research in topics: Placement & CONTEST. The author has an hindex of 15, co-authored 35 publications receiving 866 citations. Previous affiliations of Myung-Chul Kim include University of Michigan.

SimPL: An Effective Placement Algorithm

Abstract: We propose a self-contained, flat, quadratic global placer that is simpler than existing placers and easier to integrate into timing-closure flows It maintains lower-bound and upper-bound placements that converge to a final solution The upper-bound placement is produced by a novel look-ahead legalization algorithm Our placer SimPL outperforms mPL6, FastPlace3, NTUPlace3, APlace2, and Capo simultaneously in runtime and solution quality, running 710 times faster than mPL6 (when using a single thread) and reducing wirelength by 3% on the ISPD 2005 benchmark suite More significant improvements are achieved on larger benchmarks The new algorithm is amenable to parallelism, and we report empirical studies with SSE2 instructions and up to eight parallel threads

SimPL: an effective placement algorithm

Abstract: We propose a self-contained, flat, force-directed algorithm for global placement that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel rough legalization algorithm. Our placer SimPL outperforms mPL6, NTUPlace3, FastPlace3, APlace2 and Capo simultaneously in runtime and solution quality, running 6.4 times faster than mPL6 and reducing wirelength by 2% on the ISPD 2005 benchmark suite.

A SimPLR method for routability-driven placement

Abstract: Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend global placement to (i) spread cells apart in congested areas, and (ii) move cells together in less-congested areas to ensure short, routable interconnects and moderate runtime. While previous work adds isolated steps to global placement, our SIMultaneous PLace-and-Route tool SimPLR integrates a layer- and via-aware global router into a leading-edge, force-directed placer. The complexity of integration is mitigated by careful design of simple yet effective optimizations. On the ISPD 2011 Contest Benchmark Suite, with the official evaluation protocol, SimPLR outperforms every contestant on every benchmark.

Progress and challenges in VLSI placement research

Abstract: Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.

MAPLE: multilevel adaptive placement for mixed-size designs

Abstract: We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local Refinement (ProLR) helps mitigate disruptions in wirelength that we observed in leading placers. Our placer MAPLE outperforms published empirical results --- RQL, SimPL, mPL6, NTUPlace3, FastPlace3, Kraftwerk and APlace3 -- across the ISPD 2005 and ISPD 2006 benchmarks, in terms of official metrics of the respective contests.

Modern microprocessor built from complementary carbon nanotube transistors

Abstract: Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems. A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.

Limits on fundamental limits to computation

Abstract: To evaluate the promise of potential computing technologies, this review examines a wide range of fundamental limits, such as to performance, power consumption, size and cost, from the device level to the system level. Computers have evolved at a remarkable rate, with improvements over the past fifty years roughly in line with Gordon Moore's prescient observation that the number of transistors in a dense integrated circuit would double approximately every two years. The rate of 'Moore scaling' is slowing down and other physical limits are looming, but new technologies such as carbon nanotubes, graphene and quantum computation are on the way. In this Review, Igor Markov takes a fresh look at the fundamental limits at various levels, from devices to complete systems, and compares loose and tight limits. Markov argues that the study of the limits of fundamental limits to computation can lead to new insights for emerging technologies. An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

Vlsi Physical Design From Graph Partitioning To Timing Closure

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