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N. B. Jones

Bio: N. B. Jones is an academic researcher from University of Leicester. The author has contributed to research in topics: Bandwidth (computing) & Digital signal processing. The author has an hindex of 1, co-authored 1 publications receiving 3 citations.

Papers
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Journal ArticleDOI
TL;DR: An alternative DMA-based scheme is presented for efficient transfer of data between processors for demanding applications where real-time performance and maximum system bandwidth are essential.

3 citations


Cited by
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Patent
19 Jun 2002
TL;DR: In this paper, an electronic system, an integrated circuit and a method for display are described, where the electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder.
Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

14 citations

Patent
27 Jan 2011
TL;DR: In this article, an electronic system, an integrated circuit and a method for display are described, and an arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority.
Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

8 citations

Journal ArticleDOI
TL;DR: The system described herein attempts to address the need for integration of DSP implementation Issues into the mainstream by packing in all basic features at low cost, without compromising on performance, and with special emphasis on simplicity and user-friendliness.
Abstract: DSP computing processes and processors are having an impact similar to the effect the microprocessor had on computing. The speed with which DSP has penetrated myriad applications is amazing. The integration of DSP implementation Issues into the mainstream is however hindered by the unattractiveness of commercial development tools for lower end users. The system described herein attempts to address this need by packing in all basic features at low cost, without compromising on performance, and with special emphasis on simplicity and user-friendliness.