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Author

N. Badereddine

Other affiliations: Leonardo, Infineon Technologies, Intel Mobile Communications  ...read more
Bio: N. Badereddine is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & Low-power electronics. The author has an hindex of 9, co-authored 39 publications receiving 303 citations. Previous affiliations of N. Badereddine include Leonardo & Infineon Technologies.

Papers
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Proceedings ArticleDOI
16 Oct 2006
TL;DR: It is shown that taking care of high current levels during the test cycle is highly relevant to avoid noise phenomena such as IR-drop or ground bounce and a solution based on power-aware assignment of don't care bits in deterministic test patterns is proposed.
Abstract: Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution

61 citations

Proceedings ArticleDOI
24 May 2010
TL;DR: A comparative study on the effects of resistive-bridging defects in the SRAM core- cells, considering different technology nodes, shows malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.
Abstract: In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.

30 citations

Proceedings ArticleDOI
16 Oct 2006
TL;DR: Results show that the proposed structural-based power-aware X-filling technique provides the best tradeoff between peak power reduction and increase of test sequence length.
Abstract: Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length.

24 citations

Journal ArticleDOI
TL;DR: The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits and shows that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.
Abstract: Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

16 citations

Book ChapterDOI
01 Jan 2007
TL;DR: The issues of excessive peak power during scan testing are discussed and the importance of reducing peak power particularly during the test cycle so as to avoid noise phenomena such as IR-drop or Ground Bounce is highlighted.
Abstract: Scan technology increases the switching activity well beyond that of the functional operation of an IC In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (ie between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm Experimental evidence and practical implications of the proposed solution are given at the end of the paper For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool Fault coverage and test time are left unchanged by the proposed solution

15 citations


Cited by
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Proceedings ArticleDOI
01 Mar 2012
TL;DR: Low power dissipation during test application is becoming increasingly important in today's V LSI systems design and is a major goal in the future development of VLSI design.
Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.

200 citations

Book
20 Nov 2007
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Abstract: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.

151 citations

Proceedings ArticleDOI
Srivaths Ravi1
01 Oct 2007
TL;DR: Concerns and challenges in power-aware test are highlighted, various practices drawn from both academia and industry are surveyed, and critical gaps that need to be addressed in the future are pointed out.
Abstract: Power-aware test is increasingly becoming a major manufacturing test consideration due to the problems of increased power dissipation in various test modes as well as test implications that arise due to the usage of various low-power design technologies in devices today. Several challenges emerge for test engineers and test tool developers, including (and not restricted to) understanding of various concerns associated with power-aware test, development of power-aware design-for-test (DFT), automatic test pattern generation (ATPG) techniques, and test power analysis flows, evaluation of their efficacy and ensuring easy/rapid deployment. This paper highlights concerns and challenges in power-aware test, surveys various practices drawn from both academia and industry, and points out critical gaps that need to be addressed in the future.

98 citations

Journal ArticleDOI
TL;DR: The proposed architecture reorders scan cells based on their placement during physical design to reduce circuit switching activity by limiting it into a specific region and helps magnify Trojan contribution to the total circuit transient power by increasing Trojan-to-circuit switching activity (TCA) and Trojan- to-circuits power consumption (TCP).
Abstract: Government agencies and the semiconductor industry have raised serious concerns about malicious modifications to the integrated circuits. The added functionality known as hardware Trojan poses major detection and isolation challenges. This paper presents a new hardware trust architecture to magnify functional Trojans activity. Trojan detection resolution depends on Trojan activity directly and circuit activity reversely. The proposed architecture reorders scan cells based on their placement during physical design to reduce circuit switching activity by limiting it into a specific region. This helps magnify Trojan contribution to the total circuit transient power by increasing Trojan-to-circuit switching activity (TCA) and Trojan-to-circuit power consumption (TCP). The proposed technique aims to improve the efficiency of power-based side-channel signal analysis techniques for detecting hardware Trojans. Our simulation results demonstrate the efficiency of the method in significantly increasing TCA and TCP.

83 citations