N. Balasubramanian

Bio: N. Balasubramanian is an academic researcher from Singapore Science Park. The author has contributed to research in topics: MOSFET & High-κ dielectric. The author has an hindex of 30, co-authored 138 publications receiving 3491 citations. Previous affiliations of N. Balasubramanian include Massachusetts Institute of Technology & Agency for Science, Technology and Research.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well

Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate

Abstract: Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 A and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric

Abstract: An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied The surface SiH4 annealing was implemented prior to HfO2 deposition X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition The electrical measurement shows that an equivalent oxide thickness of 135A and a leakage current of 116×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

Abstract: This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The strained N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of SiC in the S/D regions. The carbon mole fraction incorporated is 1.3%. Lattice mismatch of /spl sim/0.65% between SiC and Si results in horizontal tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The conduction band offset /spl Delta/E/sub c/ between the SiC source and the strained-Si channel also contributes to increased electron injection velocity from the source. Implementation of the SiC stressors provides significant drive current I/sub DS/ enhancement in the N-MOSFETs. I/sub DS/ enhancement of 50% was observed for a gate length of 50 nm.

Synthesis and Surface Engineering of Complex Nanostructures by Atomic Layer Deposition

Abstract: Atomic layer deposition (ALD) has recently become the method of choice for the semiconductor industry to conformally process extremely thin insulating layers (high-k oxides) onto large-area silicon substrates. ALD is also a key technology for the surface modification of complex nanostructured materials. After briefly introducing ALD, this Review will focus on the various aspects of nanomaterials and their processing by ALD, including nanopores, nanowires and -tubes, nanopatterning and nanolaminates as well as low-temperature ALD for organic nanostructures and biomaterials. Finally, selected examples will be given of device applications, illustrating recent innovative approaches of how ALD can be used in nanotechnology.

25th Anniversary Article: Semiconductor Nanowires – Synthesis, Characterization, and Applications

Abstract: Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

Memory effects in complex materials and nanoscale systems

Abstract: Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results