N. Rajeev Pankaj
Bio: N. Rajeev Pankaj is an academic researcher from VIT University. The author has contributed to research in topics: Multiplier (economics) & Logic synthesis. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.
TL;DR: This new reversible multiplier was used to design 4-bit reversible multiplier and the results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs.
Abstract: Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.
01 Mar 2017
TL;DR: This work has explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation.
Abstract: Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.
••01 Jan 2021
TL;DR: In this paper, the authors proposed an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs.
Abstract: Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.