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N. Vijaykrishnan
Researcher at Pennsylvania State University
Publications - 213
Citations - 8574
N. Vijaykrishnan is an academic researcher from Pennsylvania State University. The author has contributed to research in topics: Energy consumption & Cache. The author has an hindex of 52, co-authored 191 publications receiving 8367 citations.
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Journal ArticleDOI
Analysis of error recovery schemes for networks on chips
Srinivasan Murali,Theocharis Theocharides,N. Vijaykrishnan,Mary Jane Irwin,Luca Benini,G. De Micheli +5 more
TL;DR: This article explores error control mechanisms at the data link and network layers and presents the schemes' architectural details to investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Proceedings ArticleDOI
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Chrysostomos Nicopoulos,Dongkook Park,Jongman Kim,N. Vijaykrishnan,Mazin Yousif,Chita R. Das +5 more
TL;DR: A novel unified buffer structure, called the dynamic virtual channel regulator (ViChaR), which dynamically allocates virtual channels and buffer resources according to network traffic conditions and maximizes throughput by dispensing a variable number of VCs on demand is introduced.
Proceedings ArticleDOI
Dynamic management of scratch-pad memory space
TL;DR: A compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework that uses both loop and data transformations is proposed that indicates significant reductions in data transfer activity between SPM and off-chip memory.
Proceedings ArticleDOI
A low latency router supporting adaptivity for on-chip interconnects
TL;DR: This work simulates and evaluates the proposed router architecture which utilizes adaptive routing while maintaining low latency, and results indicate that the architecture is effective in balancing the performance and energy of NoC designs.
Proceedings ArticleDOI
Exploring Fault-Tolerant Network-on-Chip Architectures
TL;DR: This paper examines the impact of transient failures on the reliability of on-chip interconnects and develops comprehensive counter-measures to either prevent or recover from them and proposes several novel schemes to remedy various kinds of soft error symptoms.