Nagendra Krishnapura

Bio: Nagendra Krishnapura is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Operational amplifier & Companding. The author has an hindex of 18, co-authored 78 publications receiving 1179 citations. Previous affiliations of Nagendra Krishnapura include Agere Systems & Alcatel-Lucent.

Ieee transactions on circuits and systems—ii: express briefs

Abstract: The explosive demand in wireless-capable devices, especially with the proliferation of multiple standards, indicates a great opportunity for adoption of wireless technology at a mass-market level. The communication devices of both today and the future will have not only to allow for a variety of applications, supporting the transfer of characters, audio, graphics, and video data, but they will also have to maintain connection with many other devices rather than with a single base station, in a variety of environments. Moreover, to provide various services from different wireless communication standards with higher capacities and higher data-rates, fully integrated and multifunctional wireless devices will be required. Multifunctional circuits and systems can be made profitable by a large scale of integration, elimination of external components, reduction of silicon area, and extensive reuse of resources. Integration of (Bi)CMOS transceiver RF front-end and analog baseband circuits with computing CMOS circuits on the same silicon chip further reduces costs of multifunctional mobile devices. However, as batteries continue to determine the lifetime and size of mobile equipment, further extension of capabilities of wearable and wireless devices will depend critically on the integrated circuits and systems solutions. The demand for multifunctional and multi-mode wireless-capable devices is accompanied by many significant challenges at system, circuit, and technology levels. In the Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications, we are looking for circuits and systems solutions for multiple communication standards. Examples of topics qualifying for the special issue include: • Adaptive radio circuits and systems • Multifunctional multistandard multi-band circuits and systems • Software-defined radio circuits and systems • Cognitive radio circuits and systems • Low-voltage low-power RF and analog circuits for future generations wireless systems • Ultra Wide Band circuits and systems

A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications

Abstract: We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.

A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS

Abstract: A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-/spl mu/m technology occupies 0.09 mm/sup 2/; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV/sub pk/ single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input.

System and method for orthogonal frequency division multiplexed optical communication

Abstract: A system for optical communication send optical signals over a plurality of wavelength channels. Each wavelength channel comprises a number of orthogonal subchannel frequencies which are spaced apart from one another by a predetermined amount. Each of the subchannel frequencies is modulated with data from a data stream. The data modulation scheme splits a subchannel frequency code into H and V components, and further processes the components prior to modulation with data. The various data-modulated subchannels are then combined into a single channel for transmission. The received signals are detected and demodulated with the help of a symbol timing recovery module which establishes the beginning and end of each symbol. A polarization mode distortion compensation module at the receiver is used to mitigate the effects to polarization more distortion in the fiber.

A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS

Abstract: An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of $LC$ or transmission line-based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter’s order while keeping the bandwidth constant and fine tuning is implemented by changing the filter’s bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13 $\mu \text{m}$ CMOS process demonstrates a delay tuning range of 250 ps–1.7-ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a DBW of 3.4 and a delay per unit area of 5.8 $\mathrm {ns/mm^{2}}$ . The filter has a worst case noise figure of 23 dB, and −40 dB intermodulation (IM3) distortion for 37 mVppd inputs. The chip occupies an active area of 0.6 mm2, and dissipates 112 mW–364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced $\mathrm {\lambda _{fmax}}/2$ apart shows ±90° beam steering off broadside.

Design Of Analog Cmos Integrated Circuits

Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

Design Of Analog Cmos Integrated Circuits

Abstract: Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

Methods and apparatus for measuring analytes using large scale fet arrays

Abstract: An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

LLR-Based Successive Cancellation List Decoding of Polar Codes

Abstract: We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties that simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared with a log-likelihood domain implementation, requires less irregular and smaller memories. This simplification, together with the gains in the metric sorter, lead to $ 56\%$ to $137\%$ higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large block-lengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.