Naoharu Sugiyama

Bio: Naoharu Sugiyama is an academic researcher from Toshiba. The author has contributed to research in topics: Electron mobility & MOSFET. The author has an hindex of 37, co-authored 142 publications receiving 4908 citations. Previous affiliations of Naoharu Sugiyama include National Institute of Advanced Industrial Science and Technology.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

Abstract: A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

Abstract: We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.

Si-SiGe semiconductor device and method of fabricating the same

Abstract: A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.

A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs

Abstract: A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, ie, SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs) This fabrication technique is based on the high-temperature oxidation of the SGOI layers with a lower Ge fraction It is found that Ge atoms are rejected from the oxide and condensed in the SGOI layers The conservation of the total amount of Ge atoms in the SGOI layer is confirmed by structural and compositional analyses of dry-oxidized SGOI layers at 1050°C of different initial thicknesses and oxidation times Using this technique, a 16-nm-thick SGOI layer with the Ge fraction as high as 057 is successfully obtained The Ge profiles across the SGOI layers are quite uniform and the layers are almost completely relaxed Significant dislocation generation in the SGOI layer is not observed after the oxidation This is a promising technique for application to sub-100 nm fully-depleted silicon-on-insulator (SOI) MOSFETs with strained-Si or SiGe channels

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

High-performance thin-film transistors using semiconductor nanowires and nanoribbons

Abstract: Thin-film transistors (TFTs) are the fundamental building blocks for the rapidly growing field of macroelectronics. The use of plastic substrates is also increasing in importance owing to their light weight, flexibility, shock resistance and low cost. Current polycrystalline-Si TFT technology is difficult to implement on plastics because of the high process temperatures required. Amorphous-Si and organic semiconductor TFTs, which can be processed at lower temperatures, but are limited by poor carrier mobility. As a result, applications that require even modest computation, control or communication functions on plastics cannot be addressed by existing TFT technology. Alternative semiconductor materials that could form TFTs with performance comparable to or better than polycrystalline or single-crystal Si, and which can be processed at low temperatures over large-area plastic substrates, should not only improve the existing technologies, but also enable new applications in flexible, wearable and disposable electronics. Here we report the fabrication of TFTs using oriented Si nanowire thin films or CdS nanoribbons as semiconducting channels. We show that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process. Our approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).

Superior mechanical flexibility of phosphorene and few-layer black phosphorus

Abstract: Recently, fabricated two dimensional (2D) phosphorene crystal structures have demonstrated great potential in applications of electronics. Mechanical strain was demonstrated to be able to significantly modify the electronic properties of phosphorene and few-layer black phosphorus. In this work, we employed first principles density functional theory calculations to explore the mechanical properties of phosphorene, including ideal tensile strength and critical strain. It was found that a monolayer phosphorene can sustain tensile strain up to 27% and 30% in the zigzag and armchair directions, respectively. This enormous strain limit of phosphorene results from its unique puckered crystal structure. We found that the tensile strain applied in the armchair direction stretches the pucker of phosphorene, rather than significantly extending the P-P bond lengths. The compromised dihedral angles dramatically reduce the required strain energy. Compared to other 2D materials, such as graphene, phosphorene demonstrates superior flexibility with an order of magnitude smaller Young's modulus. This is especially useful in practical large-magnitude-strain engineering. Furthermore, the anisotropic nature of phosphorene was also explored. We derived a general model to calculate the Young's modulus along different directions for a 2D system.