N
Natalia Seoane
Researcher at University of Santiago de Compostela
Publications - 89
Citations - 1027
Natalia Seoane is an academic researcher from University of Santiago de Compostela. The author has contributed to research in topics: Monte Carlo method & MOSFET. The author has an hindex of 14, co-authored 84 publications receiving 793 citations. Previous affiliations of Natalia Seoane include University of Santiago, Chile & Swansea University.
Papers
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Journal ArticleDOI
FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
Daniel Nagy,Guillermo Indalecio,Antonio J. Garcia-Loureiro,Muhammad A. Elmessary,Karol Kalna,Natalia Seoane +5 more
TL;DR: In this article, the performance, scalability, and resilience of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools.
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Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors
TL;DR: In this paper, the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors has been investigated using the nonequilibrium Green's function formalism.
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Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques
Asen Asenov,Andrew R. Brown,Gareth Roy,Binjie Cheng,Craig Alexander,Craig Riddet,Urban Kovac,Antonio Martinez,Natalia Seoane,Scott Roy +9 more
TL;DR: In this paper, the authors present models and tools developed and used by the Device Modelling Group at the University of Glasgow to study statistical variability introduced by the discreteness of charge and matter in contemporary and future nano-CMOS transistors.
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Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
Antonio J. Garcia-Loureiro,Natalia Seoane,Manuel Aldegunde,R. Valin,Asen Asenov,Antonio Martinez,Karol Kalna +6 more
TL;DR: Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using the new, second-order differential (SOD) scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids.
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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
Daniel Nagy,Gabriel Espineira,Guillermo Indalecio,Antonio J. Garcia-Loureiro,Karol Kalna,Natalia Seoane +5 more
TL;DR: Nanosheet (NS) and nanowire FET architectures scaled to a gate length of 16 nm and below are benchmarked against equivalent FinFETs and the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing.