Natesan Venkateswaran

TL;DR: A canonical first-order delay model that takes into account both correlated and independent randomness is proposed, and the first incremental statistical timer in the literature is reported, suitable for use in the inner loop of physical synthesis or other optimization programs.

TL;DR: A novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size, and it is shown that for large industrial designs with 442,000 gates, the algorithm computes all edge criticalities in less than 160 seconds.

TL;DR: In this paper, an approach for covering multiple selective timing corners in a single statistical timing run is described, where a single timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions.

TL;DR: In this article, a method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times is proposed, comprising the steps of using a computer, identifying one or more pairs of asserted arrival time for which one or multiple correlations exist, propagating to each of the one or several pairs of assertion times a timing value dependent on the one-or more correlations, and performing a subsequent common path pessimism removal analysis for at least one test during which the timing value depends on the correlations.

TL;DR: An abstraction based multi-phase method for VLSI chip floorplanning is described in this article, where annotations generated during abstraction are presented as floorplan constraints which account for abstracted data.