Navakanta Bhat

Bio: Navakanta Bhat is an academic researcher from Indian Institute of Science. The author has contributed to research in topics: Thin film & Gate dielectric. The author has an hindex of 26, co-authored 302 publications receiving 2804 citations. Previous affiliations of Navakanta Bhat include Stanford University & Indian Institute of Technology Bombay.

A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

Abstract: A high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects 015 /spl mu/m transistors (L/sub gate/=015/spl plusmn/004 /spl mu/m) are optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability Copper has been integrated into the back-end to provide low resistance interconnects Critical layer pitches for the technology are summarized and enable fabrication of 76 /spl mu/m/sup 2/ 6T SRAM cells

Transistors based on two-dimensional materials for future integrated circuits

Abstract: Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. This Review examines the development of field-effect transistors based on two-dimensional materials and considers the challenges that need to be addressed for the devices to be incorporated into very large-scale integration (VLSI) technology.

Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region

Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).

MoSe2 nanoflakes based chemiresistive sensors for ppb-level hydrogen sulfide gas detection

Abstract: Detection and quantification of hydrogen sulfide (H2S) gas is important as it influences directly human health, our environment, and operations of several industries including food and beverages, oil, construction, and medicine. It also acts as biomarker in diagnosis of halitosis at early stage. We report herein liquid exfoliated MoSe2 nanoflakes based stable chemiresistive H2S gas sensor which operate at moderate temperature of 200℃. The response of p-type MoSe2 gas sensor device (when operated in ambient environment) was found to be varying between 15.87%–53.04% when the concentration of H2S was varied between 50 ppb – 5.45 ppm. The response of the device decreases when the measurements were done in synthetic air environment and it varies between 7.13%–19.87% for the concentration range of 500 ppb - 5.45 ppm. The response (%), recovery rate (%), hysteresis, experimental lowest detection limit etc. of the device suggest that the device performs better when operated in ambient than in synthetic air which suggest its real time device application. The response time and recovery time of the sensor are 15 s and 43 s respectively for 100 ppb of H2S. The sensor performance was found to be highly repeatable with sensitivity of 5.57%/ppm of H2S. The theoretical limit of detection and limit of quantization of the device were found to be 6.73 ppb and 22.44 ppb respectively. Based on chemical analysis, a plausible mechanism based on charge transfer phenomenon has been proposed for this sensor.

Micromachined High-Resolution Accelerometers

Abstract: In this paper, we review the high-resolution, micromachined accelerometers by enunciating the development of their mechanical components, the electronic circuitry and the microfabrication processes. A survey of the literature suggests that the research in this area is mostly focused on improving microfabrication and electronic circuitry. The resolution of the accelerometers is dependent on the sensitivity of the mechanical components as well as the ability of the electronic circuitry in suppressing the noise. The noise comes from mechanical components as well as electronic circuitry and plays a detrimental role in achieving high resolution. This is reviewed in this paper after explaining the working principles of selected high-resolution micromachined accelerometers. Sensing acceleration by measuring the change in capacitance is widely used but it has many complications. These are discussed in detail by presenting various techniques for sensing capacitance. The microfabrication processes that dictate the design are reviewed by tracking the evolution of high-resolution accelerometers found in the literature and comparing their sensitivities and resolutions. This paper gives an account of the significant accomplishments, some challenges for the future, and a few novel concepts in achieving high resolution of the order of a millionth of g, the acceleration due to gravity.

The Design and Analysis of Experiments

Abstract: THE DESIGN AND ANALYSIS OF EXPERIMENTS. By Oscar Kempthorne. New York, John Wiley and Sons, Inc., 1952. 631 pp. $8.50. This book by a teacher of statistics (as well as a consultant for \"experimenters\") is a comprehensive study of the philosophical background for the statistical design of experiment. It is necessary to have some facility with algebraic notation and manipulation to be able to use the volume intelligently. The problems are presented from the theoretical point of view, without such practical examples as would be helpful for those not acquainted with mathematics. The mathematical justification for the techniques is given. As a somewhat advanced treatment of the design and analysis of experiments, this volume will be interesting and helpful for many who approach statistics theoretically as well as practically. With emphasis on the \"why,\" and with description given broadly, the author relates the subject matter to the general theory of statistics and to the general problem of experimental inference. MARGARET J. ROBERTSON

Phd by thesis

Abstract: Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

Damascene Copper electroplating for chip interconnections

Abstract: Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Damascene copper electroplating for chip interconnections

Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.