From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

Recent directions in netlist partitioning: a survey

The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) architectures that have been proposed recently for system-on-chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called xpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented In the work, showing the powerful design space exploration capabilities of the proposed methodology and tools.

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NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element. Therefore, for any given data element or node in the list structure, we can talk in terms of a next element and a previous element.

Graphs and Digraphs

We survey results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.

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Spanning Trees and Spanners

The VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. In this paper, we propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu floorplanning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperatures to reduce running time. A temperature adjustment scheme is designed to give smooth transitions between different stages of simulated annealing. Experimental results show that our approach performs well.

Integrated floorplanning and interconnect planning

Integrated Circuit (IC) has transformed our society into an information society. It impacts all walks of life and promises to be even more dominating with the arrival of information superhighway. This revolutionary development and widespread use of ICs has been one of the greatest achievements of the humankind. Since its inception in 1960’s, IC technology has evolved from in-tegration of a few transistors in Small Scale Integration (SSI) to integration of millions of transistors in Very Large Scale Integration (VLSI) chips currently in use. Early IC’s only had a couple of gates or a flip-flop. Some IC’s were simply a single transistor along with a resistor network to perform a logic function. In a period of three and a half decades, there have been four generations of IC’s with the number of transistors on a single chip growing from a few to over 10 million. This rapid growth in integration technology has been made possible by automation of various steps involved in design and fabrication of VLSI chips.

VLSI Physical Design Automation

A sliding, radial compression seal is provided between the main gauge casing and a movable blow-out closure element, in a fluid-filled pressure gauge, with yieldable retention of the closure in its normal case closing position. The closure seal insures maintenance of an effective fluig-tight seal of the gauge housing under normal conditions while permitting ready movement of the closure for release of unusual internal pressures.

Routing in the Third Dimension

A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-re-floorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.

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Naveed A. Sherwani

Papers

Algorithms for VLSI Physical Design Automation

Integrated floorplanning and interconnect planning

VLSI Physical Design Automation

Routing in the Third Dimension

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs