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Author

Neha Bansal

Other affiliations: GLA University
Bio: Neha Bansal is an academic researcher from Chitkara University. The author has contributed to research in topics: Digital watermarking & Gaussian noise. The author has an hindex of 5, co-authored 14 publications receiving 90 citations. Previous affiliations of Neha Bansal include GLA University.

Papers
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Proceedings ArticleDOI
01 Nov 2015
TL;DR: The general architecture of modern OCR system with details of each module is discussed, and Moore neighborhood tracing is applied for extracting boundary of characters and then chain rule for feature extraction.
Abstract: Artificial intelligence, pattern recognition and computer vision has a significant importance in the field of electronics and image processing. Optical character recognition (OCR) is one of the main aspects of pattern recognition and has evolved greatly since its beginning. OCR is a system which recognized the readable characters from optical data and converts it into digital form. Various methodologies have been developed for this purpose using different approaches. In this paper, general architecture of modern OCR system with details of each module is discussed. We applied Moore neighborhood tracing for extracting boundary of characters and then chain rule for feature extraction. In the classification stage for character recognition, SVM is trained and is applied on suitable example.

25 citations

Proceedings Article
11 Mar 2015
TL;DR: In this work, watermarking has been done using LSB technique, DCT transform and DWT transform, and parameters are compared for various noises like Gaussian noise, Poisson noise, Salt and Pepper noise and Speckle noise.
Abstract: In one's day to day life; internet is growing and became an important part. Digital content can easily be downloaded, copied or edited. Digital content can be secured by various ways. Digital Watermarking is one of the methods for the protection of Digital Content. Digital Watermarking is a method by which data can be secured by hiding data in any image which can work as a carrier image. The carrier image is also known as cover image. Watermarking is an interactive method to protect and identify the digital data. It permits various types of watermarks to be hidden in digital data e.g. image, audio and video. In this work, watermarking has been done using LSB technique, DCT transform and DWT transform. These techniques are compared on the basis of peak signal to noise ratio (PSNR) and normalized correlation (NC). Parameters are compared for various noises like Gaussian noise, Poisson noise, Salt and Pepper noise and Speckle noise.

20 citations

Proceedings ArticleDOI
01 Nov 2014
TL;DR: This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

14 citations

Proceedings ArticleDOI
14 Nov 2014
TL;DR: This paper presents and compares the LSBW method using different bit positions and evaluates parameters on the basis of various parameters like Mean Square Error, Peak Signal to Noise Ratio and Normalized Cross Correlation for various attacks.
Abstract: Watermarking is a method to protect the data and to authenticate the digital content. Watermarking is required due to the emergence of usage of internet in one's day to day life. As the usage of digital content is growing rapidly, there are many instances where data is insecure. Watermarking is a process to hide data for authorization purpose. Watermarking is the best way to secure the digital content. Watermarking can be done by various methods. Least Significant Bit Watermarking (LSBW) method is one of them. In this method, the pixel values of the image are converted in to binary and the information is concealed in the bits of the pixel values. This paper presents and compares the LSBW method using different bit positions. Comparison for these bit positions is done on the basis of various parameters like Mean Square Error, Peak Signal to Noise Ratio and Normalized Cross Correlation. These parameters are evaluated for various attacks like Gaussian Noise, Poisson Noise, Salt a Pepper Noise and Speckle Noise.

9 citations

Journal ArticleDOI
TL;DR: This work is going to design capacitance scaling based low power ROM design, and in order to test the compatibility of this ROM design with latest i7 Processor, it is operating this ROM with frequencies supported by i7 processor.
Abstract: An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

7 citations


Cited by
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01 Jan 2006
TL;DR: After you change your VT Google password, you will be unable to log on to VT Google Apps services including Mail, Drive, Groups, etc.
Abstract: IT Status "Password doesn't match" error. 4Help is aware that after you change your VT Google password, you will be unable to log on to VT Google Apps services including Mail, Drive, Groups, etc. 4Help is notifying the appropriate people. 12:00 Noon: Engineers have found a backlog on Google password replication. Once the backlog clears you should be able to log on with your changed password that you set earlier. You may be able to log on with your old VT Google password until the system catches up and syncs the new password. Service Degraded Service Degraded [Resolved] Created: Thu, 04/14/2016 11:20am Resolved: Fri, 04/15/2016 1:16pm Duration: 1 day 1 hour 56 min 1734 Views Source URL: https://computing.vt.edu/content/google-0

312 citations

Journal ArticleDOI
TL;DR: In this article, a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA) is presented.
Abstract: The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

75 citations

Journal ArticleDOI
Chong Yu1
03 Apr 2020
TL;DR: This paper proposes the novel end-to-end framework to extend the generative adversarial network application to data hiding area and shows compelling performance and advantages over the current state-of-the-art methods in data hiding applications.
Abstract: Recently, the generative adversarial network is the hotspot in research and industrial areas. Its application on data generation is the most common usage. In this paper, we propose the novel end-to-end framework to extend its application to data hiding area. The discriminative model simulates the detection process, which can help us understand the sensitivity of the cover image to semantic changes. The generative model is to generate the target image which is aligned with the original cover image. An attention model is introduced to generate the attention mask. This mask can help to generate a better target image without perturbation of the spotlight. The introduction of cycle discriminative model and inconsistent loss can help to enhance the quality of the generated target image in the iterative training process. The training dataset is mixed with intact images and attacked images. The mix training process can further improve robustness. Through the qualitative, quantitative experiments and analysis, this novel framework shows compelling performance and advantages over the current state-of-the-art methods in data hiding applications.

50 citations

Journal ArticleDOI
TL;DR: From the experimental results, it is shown that this invisible hybrid watermarking approach is robust against—rotation, JPEG compression, salt and pepper noise, Gaussian noise, speckle noise and Poisson noise.
Abstract: Digital image watermarking is a technique to protect copyright of the image owner in the world of digital communication, and robustness is the major property to be addressed effectively. We propose an invisible hybrid watermarking scheme which is composed of blind and non-blind watermarking techniques. First, blind scheme is used as inner watermarking scheme and then non-blind watermarking scheme as outer watermarking scheme. A secret binary image is taken as a watermark and is embedded in an inner cover image using discrete wavelet transformation (DWT) with the help of the blind watermarking scheme in association with predefined binary digit sequence block and gain factor $${\varvec{\upalpha }}$$ to get inner watermarked image. Then, this inner watermarked image is embedded into an outer cover image using DWT and singular value decomposition by non-blind watermarking technique to get hybrid watermarked image. On the contrary, to extract the secret binary image, first non-blind watermark extraction and then blind watermark extraction techniques are used. From the experimental results, it is shown that this hybrid watermarking approach is robust against—rotation, JPEG compression, salt and pepper noise, Gaussian noise, speckle noise and Poisson noise.

47 citations

Journal ArticleDOI
TL;DR: This paper proposes an efficient steganography scheme based on sample comparison in Discrete Wavelet Transform (DWT) domain where the cover audio is decomposed into several multi sub-bands, and then selected coefficients of details are changed by a threshold value depending on the embedding cipher image bit.
Abstract: Steganography is the technique of hiding any secret information like text, image or video behind a cover file. Audio steganography is one of the widespread data hiding techniques that embeds secret data in audio signals. The secret data is hidden in a way that unauthorized people are not aware of the existence of the embedded data and without changing the quality of the audio signal (cover audio). Data hiding in audio signals has various applications such as protection of copyrighted audio signals, secret communication, hiding data that may influence the security and safety of governments and personnel. This paper proposes an efficient steganography scheme based on sample comparison in Discrete Wavelet Transform (DWT) domainwhere the cover audio is decomposed into several multi sub-bands, and then selected coefficients of details are changed by a threshold value depending on the embedding cipher image bit. This approach employs an original image component to perform RSA encryption on it, then cipher bits are embedded in the details components of the audio signal according to a predetermined threshold value. The performance of the algorithm has been estimated extensively against attacks, and simulation results are presented to prove the robustness of the proposed algorithm.

35 citations