Nguyen My Qui

Bio: Nguyen My Qui is an academic researcher from National Taiwan University of Science and Technology. The author has contributed to research in topics: Double data rate & Phase-locked loop. The author has an hindex of 2, co-authored 2 publications receiving 9 citations.

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

Abstract: An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely −0.157 to 0.137 LSB, −0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Abstract: This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores.

128-channel high-linearity resolution- adjustable time-to-digital converters for LiDAR applications: software predictions and hardware implementations

Abstract: This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in a good agreement and show that the proposed design has great potential for multichannel applications; the averaged DNL_(pk-pk) and INL_(pk-pk) are close to or even less than 0.05 LSB in multichannel designs.

Linearity Theory of Stochastic Phase-Interpolation Time-to-Digital Converter

Abstract: The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only $4\times $ redundancy.

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

Abstract: The Internet of Things (IoT) refers to a network of physical devices, which collects data and processes into a system without human intervention In the commercialized market, IoT architectures are upgrading day by day to reduce data transmission costs, latency, and bandwidth usage for various application requirements The extensively available IoT architectures and their specification resist the researchers to select a system-on-chip (SoC) for heterogeneous IoT applications This paper seeks to comprehend the various IoT device specifications and their characteristics to support multiple applications Moreover, microprocessor architectures and their components are detailed to facilitate developer knowledge in advanced methodology and technology The various instructions set architectures (ISA) are implemented in a Zynq-7000 (xc7Zz20clg484-1) FPGA device to examine the feasibility of design space requirements for real-time hardware execution To select specific system-on-chip (SoC) architecture for heterogeneous IoT applications, a genetic algorithm (GA) based optimization method is implemented in MATLAB The proposed algorithm identifies the optimized SoC architecture concerning device parameters such as a clock, cache, RAM space, external storage, network support, etc Further, the confusion matrix method evaluates the proposed algorithm’s accuracy, which yields 8462% accuracy The outcome of SoCs attained through the GA are tested by analyzing their execution time and performance using various evaluation benchmarks This article helps the researchers and field engineers to comprehend the microarchitecture device configurations and to identify the superior SoC for next-generation IoT practices

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

Abstract: In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514 S/s prototype (ReDAC1) and on a 11-bit, 10.5 kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68 LSB (1.53 LSB) maximum INL, 1.54 LSB (1.0 LSB) maximum DNL, 76.4 dB (67.9 dB) THD, 79.7 dB (71.4 dB) SFDR and 71.3 dB (63.3 dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB).

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Abstract: This article proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged ${{\bf DN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$ and ${{\bf IN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$ are close to or even less than 0.05 LSB in multichannel designs.