Nicholas C. M. Fuller

Bio: Nicholas C. M. Fuller is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Copper interconnect. The author has an hindex of 22, co-authored 106 publications receiving 2124 citations. Previous affiliations of Nicholas C. M. Fuller include Alcatel-Lucent & Toshiba.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Abstract: We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Abstract: FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Diagnostics of inductively coupled chlorine plasmas: Measurement of Cl2+ and Cl+ densities

Abstract: The absolute densities of positive ions (Cl2+ and Cl+) are obtained over a 2–20 mTorr pressure range and 5–1000 W input radio-frequency rf power range in a transformer-coupled Cl2 plasma. The relative number density of Cl2+ is measured by laser-induced fluorescence. These laser-induced fluorescence data are calibrated by Langmuir-probe measurements of total positive-ion density at low powers to yield absolute values for nCl2+ and are corrected for changes in rotational temperature with rf power. In turn, the nCl2+ data are used to determine the effective-mass correction for refined Langmuir-probe measurements of the total positive-ion density. The density of Cl+ is then the difference between the total positive-ion and Cl2+ densities. For all the pressures, Cl2+ is found to be the dominant ion in the capacitively coupled regime (input powers below 100 W), while Cl+ is the dominant ion at higher powers (>300 W) of the inductively coupled regime. Experimental results are compared to those from a simple glob...

MRONLINE: MapReduce online performance tuning

Abstract: MapReduce job parameter tuning is a daunting and time consuming task. The parameter configuration space is huge; there are more than 70 parameters that impact job performance. It is also difficult for users to determine suitable values for the parameters without first having a good understanding of the MapReduce application characteristics. Thus, it is a challenge to systematically explore the parameter space and select a near-optimal configuration. Extant offline tuning approaches are slow and inefficient as they entail multiple test runs and significant human effort.To this end, we propose an online performance tuning system, MRONLINE, that monitors a job's execution, tunes associated performance-tuning parameters based on collected statistics, and provides fine-grained control over parameter configuration. MRONLINE allows each task to have a different configuration, instead of having to use the same configuration for all tasks. Moreover, we design a gray-box based smart hill climbing algorithm that can efficiently converge to a near-optimal configuration with high probability. To improve the search quality and increase convergence speed, we also incorporate a set of MapReduce-specific tuning rules in MRONLINE. Our results using a real implementation on a representative 19-node cluster show that dynamic performance tuning can effectively improve MapReduce application performance by up to 30% compared to the default configuration used in YARN.

Characterization of transformer coupled oxygen plasmas by trace rare gases-optical emission spectroscopy and Langmuir probe analysis

Abstract: Trace rare gases-optical emission spectroscopy (TRG-OES) and Langmuir probe analysis have been used to measure the electron temperature, Te , in a high-density inductively (transformer) coupled (TCP) 10 mTorr oxygen plasma as a function of the 13.56 MHz radio frequency (rf) power. The oxygen atomic densities were estimated by O-atom optical emission (8446 ?), and rare gas actinometry (Ar, 7504 ?). In the H-(inductive)-mode, Te increases from 2.6 to 3.4 eV for the low-energy electrons sampled by the Langmuir probe and from ~3.5 to 6.0 eV for the high-energy electrons sensed by TRG-OES as the rf power is increased from 120 to 1046 W. In the E-(capacitive)-mode, below 50 W, Te measured by TRG-OES increases with rf power from ~4 eV at very low power (~7 W) to ~6.1 eV at 45 W. Between the highest E-mode power (~50 W) and lowest H-mode power (~120 W), the Te measured by TRG-OES drops from 6.1 to 3.5 eV, while Te derived from Langmuir probe measurements drops only slightly from 3.0 to 2.6 eV. In the H-mode, the electron energy distribution function (EEDF) is bi-Maxwellian from ~120 to 1046 W. In the E-mode, the EEDF changes from nearly Maxwellian (possibly Druyvesteyn) at low rf powers (~7 W) to bi-Maxwellian at the higher E-mode powers (~45 W). O2 dissociation is low (~2%) at the maximum rf power density of 5.7 W cm-2 (1046 W), and this low value is attributed to the high rate of O-atom recombination on the mostly stainless-steel walls. A detailed accounting of the sources of O (8446 ?) emission revealed significant contributions from electron impact excitation from O(1 S) and dissociative excitation of O2 .

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Low dielectric constant materials.

Abstract: Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Plasma etching: Yesterday, today, and tomorrow

Abstract: The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.