A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype $1024 \times 128$ CMOS TDI image sensor is fabricated in the 0.18- $\mu \text{m}$ CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of $18.2~\textrm {mm}\times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 $\textrm {V}/\textrm {lux}\cdot \textrm {sec}$ . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems.

A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator

The present invention relates to the field of design of analog digital hybrid integrated circuit. The object of the invention is to reduce ADC conversion rate thus further reducing power consumption of the sensor while not reducing line frequency of the CMOS-TDI. To this end, a digital domain accumulative CMOS-TDI image sensor with low power consumption is provided. It includes a pixel array of n+k lines multiplied m columns, a column parallel signal pre-processing circuit, a column parallel successive approximation (SAR) ADC, a column parallel digital domain accumulator, a column parallel divider, a timing control circuit and an output shift register, wherein n+k+1 coarse quantification memory units are provided to the column parallel digital domain accumulator for storage of coarse quantification results; and memory units for storage of n times of fine quantification results are also provided, thus realizing n stages of TDI signal accumulation after accumulation of n times of fine quantification results. The invention is generally used in hybrid integrated circuit design.

Digital domain accumulative cmos-tdi image sensor with low power consumption

The present invention relates to the field of digital-analog hybrid integrated circuit design. To achieve the objective of reducing a conversion rate of an analog to digital converter (ADC) without reducing a horizontal frequency of a CMOS-TDI image sensor, and further reducing power consumption of the sensor, the technical solution adopted by the present invention is a low power consumption digital domain accumulating CMOS-TDI image sensor, comprising: a pixel array of n+k rows×m columns, a column parallel signal preprocessing circuit, a column parallel successive approximation type ADC, a column parallel digital domain accumulator, a column parallel divider, a time sequence control circuit, and an output shift register. Besides, the low power consumption digital domain accumulating CMOS-TDI image sensor also comprises: n+k+1 coarse quantification storage units that are added in the column parallel digital domain accumulator and are used for storing coarse quantification results; and a storage unit for storing n-fine quantification results. TDI signals are accumulated at n levels by accumulating and outputting the n-fine quantification results. The present invention is mainly applied to the digital-analog hybrid integrated circuit design.

Low-power consumption digital domain accumulating CMOS-TDI image sensor

A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

In image boundary detection, the common method is the threshold based on image segmentation. Traditional fixed grey threshold based on segmentation results in high false alarm and misses alarm rate. A framework of switch gaps detection based on CMOS plane is constructed, which focuses on the location and monitoring of switch gaps in high-speed railways. By the information theory, adaptive threshold selection and edge detection algorithm based on Shannon entropy are proposed. This algorithm shows low computation complexity and is adaptive to various contrast ratio of image with noise. It improves the detection precision and reliability. The efficiency of the proposed framework and the edge detection algorithm is verified by field data from Changsha Station in Beijing-Guangzhou high speed railway. The experiment results show that the efficiency of the proposed framework and edge detection algorithm based on Shannon entropy is improved.

Detection of switch gaps based on CMOS plane in high-speed railways

A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/−0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

https://iopscience.iop.org/article/10.1088/1674-4926/35/3/035005/pdf

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

The timing control circuit of 1 024×128 time-delay-integration(TDI)CMOS image sensor was designed.The synchronization of charge transfer between pixels and signal accumulation was implemented,based on along-track-rolling exposure mode and through increasing the frequency of exposure.The timing control circuits of pixel array,accumulator and column level ADC were designed and verified.I2C bus controlled variation of the related parameters.The design costs 761 standard cells,and the layout size is 125μm×160μm.Total dynamic power consumption is 40.55μW,and leakage power consumption is 10.43μW.Timing is correct and meets the requirements.The combination of timing control circuit and analog circuit implements a TDI CMOS image sensor.

Design and Implementation of Timing Control for TDI CMOS Image Sensor

A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.

Nie Kaiming

Papers

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

Design and Implementation of Timing Control for TDI CMOS Image Sensor

Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage

Research of MTF Velocity Mismatch Model for Time Delay Integration CMOS Area Image Sensors