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Showing papers by "Nils Weimann published in 2004"


Journal ArticleDOI
TL;DR: In this paper, an InGaAs-InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-/spl Omega was described.
Abstract: Return-to-zero differential phase-shift keying applications require a differential amplifier with high bandwidth, high gain, low noise, and good input impedance match. In this paper, we describe an InGaAs-InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-/spl Omega/. The input-referred current noise is less than 35 pA//spl radic/Hz over the measurement range up to 40 GHz.

45 citations


Journal ArticleDOI
TL;DR: In this article, inductively coupled plasma (ICP) was used for mesa etching of InP using Cl2/N2 chemistry with a Ni metal mask, achieving a rate of approximately 140 nm/min at a dc bias of 120 V. The effects of temperature, gas flow, chamber pressure, ICP source power, and substrate bias power on etch rate were studied.
Abstract: Inductively coupled plasma (ICP) operated in the reactive-ion etching mode is used for mesa etching of InP using Cl2/N2 chemistry with a Ni metal mask. Etch rates of approximately 140 nm/min with very smooth and vertical sidewalls are obtained at a dc bias of 120 V. The effects of temperature, gas flow, chamber pressure, ICP source power, and substrate bias power on etch rate are studied; sidewall profile and surface morphology will be discussed.

34 citations


Journal ArticleDOI
TL;DR: In this paper, a 40-Gb/s driver amplifiers were realized in 1.2/spl mu/m emitter double-heterojunction InGaAs-InP HBT (D-HBT) technology with a maximum cut-off frequency (f/sub T/) of 150 GHz and a maximum oscillation frequency ( f/sub max/) of 200 GHz.
Abstract: High-performance and compact 40-Gb/s driver amplifiers were realized in 1.2-/spl mu/m emitter double-heterojunction InGaAs-InP HBT (D-HBT) technology with a maximum cut-off frequency (f/sub T/) of 150 GHz and a maximum oscillation frequency (f/sub max/) of 200 GHz. Two-stage differential drivers feature a lumped input and fully distributed output stage and deliver a maximum differential output swing of 11.3 V peak-to-peak (V/sub pp/) at 40 Gb/s with less then 350 fs of added rms jitter and rise and fall times of about 7 ps while consuming a total power of 3 W. When biased at a lower output swing of 6.3 V/sub pp/, excellent 40-Gb/s eyes with a 7-ps fall time, 6-ps rise time, and no observable jitter deterioration compared with the input source are obtained at a reduced power consumption of 1.7 W. On-wafer measured differential S-parameters show a differential gain of 25 dB, 50 GHz bandwidth, and input and output reflection below -20 dB from 2 to 45 GHz. The amplifiers' small die size (1.0/spl times/1.7 mm), relatively low power consumption, large output swing, and ability to have dc coupled inputs and outputs enable compact 40-Gb/s optical transmitters with good eye opening for both conventional transmission formats such as nonreturn-to-zero and return-to-zero and alternative formats such as duobinary and differential phase shift keying.

33 citations


Journal ArticleDOI
TL;DR: In this article, the thermal properties of submicron InP-InGaAs-InP double heterojunction bipolar transistors (DHBTs) with emitter dimensions of A = 0.25 /spl times/ 4 /spl mu/m/sup 2.
Abstract: We studied the thermal properties of submicron InP-InGaAs-InP double heterojunction bipolar transistors (DHBTs) with emitter dimensions of A = 0.25 /spl times/ 4 /spl mu/m/sup 2/. From the temperature dependence of V/sub bc/, we measured a thermal resistance of R/sub th/ = 3.3 /spl deg/C/mW for DHBTs with ion-implanted n+-InP subcollector at room temperature, compared to a high R/sub th/ = 7.5 /spl deg/C/mW from DHBTs with conventional grown InGaAs subcollector. Two-dimensional device simulations confirm the measured results.

12 citations


Patent
03 Jun 2004
TL;DR: In this paper, the authors propose a heterobipolar transistor with a spacer ring interposed between and defining a charge carrier access path distance between the base electrode and the third layer, the path distance being within a range of between about 200 and 1000 Å.
Abstract: Apparatus comprising: a first compound semiconductor composition layer doped to have a first charge carrier polarity; a second compound semiconductor composition layer doped to have a second charge carrier polarity and located on the first layer; a third compound semiconductor composition layer doped to have the first charge carrier polarity and located on the second layer; a base electrode on the second layer; and a spacer ring interposed between and defining a charge carrier access path distance between the base electrode and the third layer, the path distance being within a range of between about 200 Å and about 1000 Å. Techniques for making apparatus. Apparatus is useful as a heterobipolar transistor, particularly for high frequency applications.

6 citations


Patent
03 Jun 2004
TL;DR: In this paper, the authors propose a heterobipolar transistor with a spacer ring interposed between and defining a charge carrier access path distance between the base electrode and the third layer, the path distance being within a range of between about 200 and 1000 Å.
Abstract: Apparatus comprising: a first compound semiconductor composition layer doped to have a first charge carrier polarity; a second compound semiconductor composition layer doped to have a second charge carrier polarity and located on the first layer; a third compound semiconductor composition layer doped to have the first charge carrier polarity and located on the second layer; a base electrode on the second layer; and a spacer ring interposed between and defining a charge carrier access path distance between the base electrode and the third layer, the path distance being within a range of between about 200 Å and about 1000 Å. Techniques for making apparatus. Apparatus is useful as a heterobipolar transistor, particularly for high frequency applications.

1 citations



Journal ArticleDOI
TL;DR: In this article, the authors show that the emitter and collector doping profile engineering is very important for transistor optimization, in particular, adjusting the low-doped emitter section to the depletion length resulted in the decrease of the series resistance and increased f/sub t/ and f/ sub max/; decreasing of the collector doping concentration and shrinking the collector thickness reduced the collector transit time.
Abstract: Our simulations show that the emitter and collector doping profile engineering is very important for the transistor optimization, in particular, adjusting the low doped emitter section to the depletion length resulted in the decrease of the emitter series resistance and increased f/sub t/ and f/sub max/; decreasing of the collector doping concentration and shrinking the collector thickness reduced the collector transit time. Accounting for the lateral diffusion of hot electrons in the device with submicron emitter was found to be important in the transistor optimization process. This effect determines the effective thickness of the emitter finger and the value of the push-out current.