Showing papers by "Nils Weimann published in 2017"

Flip-Chip Approach for 500 GHz Broadband Interconnects

Abstract: This paper presents the design and characterization of a broadband transition in the range dc to 500 GHz using the flip-chip concept. The extremely wideband performance is attained by optimizations in both process technology and electromagnetic design. On the process technology side, a thin-film process with scaled dimensions of 10 $\mu \text{m}$ for via diameter and 2 $\mu \text{m}$ bump height is employed for the chip and the carrier substrate. On the electromagnetic side, in addition to impedance matching, a detailed analysis of parasitic modes is considered for the design. The measurement results show less than 0.9-dB insertion loss per transition at 500 GHz and reflections below −18 dB over the entire dc to 500 GHz band.

Tight Focus Toward the Future: Tight Material Combination for Millimeter-Wave RF Power Applications: InP HBT SiGe BiCMOS Heterogeneous Wafer-Level Integration

Abstract: The push to conquer the sparsely used electromagnetic spectrum between 100 and 1,000 GHz, commonly known as the millimeter-wave (mmW) and sub-mmW regions, is now in full force. The current rapid development of electronic circuits and subsystems beyond 100 GHz is enabled by improvements in high-frequency semiconductor technology and packaging techniques. In this article, we highlight recent advances we have developed in heterogeneous semiconductor-material chip integration for application toward the mmW frequency bands?in essence, a waferlevel integration approach that replaces chip-to-chip connections with monolithic integration.

Manufacturable Low-Cost Flip-Chip Mounting Technology for 300–500-GHz Assemblies

Abstract: We developed a chip mounting technology suitable for low-cost assemblies in the 300–500-GHz frequency range, compatible with standard chip and submount fabrication techniques. The waveguide and transition designs are compatible with indium phosphide heterobipolar transistor millimeter-wave monolithic integrated circuit chip architecture. Increased conductor shielding in different multilayer thin-film waveguide topologies is applied to suppress radiative losses, enabling low-loss interconnects up to 500-GHz bandwidth. Standard flip-chip align-and-place equipment is used to assemble the chips onto submounts. Losses are evaluated by banded ${S}$ -parameter measurements between 10 MHz and 500 GHz. For an optimized stripline-to-stripline transition, an insertion loss of less than 1 dB was measured at 500 GHz.

An active balanced up-converter module in InP-on-BiCMOS technology

Abstract: This paper presents an active up-converter realized as hetero-integrated module in InP-on-BiCMOS technology. It consists of a fundamental Voltage Controlled Oscillator (VCO) in 0.25 μm BiCMOS technology and a frequency multiplier followed by double balanced Gilbert mixer cell in 0.8 μm transferred substrate (TS) InP-HBT technology, which is integrated on top of the BiCMOS MMIC. The fundamental VCO operates at 54 GHz. The module achieves a single-sideband (SSB) power up-conversion gain of 2.5 dB and −3.5 dB at 82 GHz and 106 GHz, respectively. It exhibits > 25 GHz IF bandwidth. To the knowledge of the authors, this is the first heterointegrated module reported so far.

EM simulation assisted parameter extraction for the modeling of transferred-substrate InP HBTs

Abstract: In this paper an electromagnetic (EM) simulation assisted parameters extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated 3D EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line (TRL) calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network is verified against measured S-parameters up to 110 GHz.

Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology

Abstract: This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

Noise modeling of transferred-substrate InP-DHBTs

Abstract: This paper addresses noise modeling of transfersubstrate indium phosphide double heterobipolar transistors (InP DHBTs). Transistors with an emitter area of 0.8 × 6 μm2 (single-finger) and 2 × 0.8 × 6 μm2 (double-finger) are measured and simulated. It turns out that the correlation of shot-noise sources is negligible for these devices, although it was found in earlier works to be essential to describe GaAs HBT noise behavior. As a result, the work provides the basis for reliable extrapolation of noise performance beyond the frequency range provided by standard noise measurement equipment.

An efficient W-band InP DHBT digital power amplifier

Abstract: This paper presents for the first time high-efficiency W-band power amplifiers (PAs), the design of which follows the digital PA (DPA) design concept. Two DPAs with different output networks have been realized: a single-band version (S-DPA) for 95 GHz and a dual-band design (D-DPA) for signal frequencies fS of 68 GHz (first band) and 76 GHz (second band), respectively. The PAs are realized as monolithic microwave-integrated circuits (MMICs) in a 0.8 μm InP DHBT transferred-substrate process. They utilize a double-emitter-finger DHBT unit cell with an emitter area of 2 × 0.8 × 6 μm3 each. In contrast to the usual W-band PAs, the proposed single-stage amplifier MMICs do not apply any special reactive matching for the transistor, which leads to very compact chip sizes of 0.27 mm2 (S-DPA) and 0.39 mm2(D-DPA). The S-DPA includes one band-pass filter (BPF) at the output with 0.6 dB insertion loss (IL) and 24 dB input return loss (RL) at the signal frequency of 95 GHz. The dual-band BPF shows 0.7 dB IL in both bands with a RL of more than 21 dB each. Applying an overdriven sinusoidal input signal to emulate digital operation the DPAs achieve a maximum output power of 14.4 dBm and power-added efficiency of 31% when using the single-band configuration. Collector efficiencies of more than 80% and the flexible multi-band operation demonstrated prove the great potential of the digital PA concept for future high-speed communications.