An efficient methodology for minimizing core supply noise in Power Delivery Networks is presented. To reduce the power supply noise, an optimal decoupling network is designed by Simulated Annealing. The cumulative impedance of Power Delivery Network is reduced using lesser number of decoupling capacitors compared to placing decoupling capacitors intuitively. The supply noise is minimized according to the requirement of system specifications and the corresponding jitter reduction is reported.

Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing

The decoupling of modern printed circuit boards introduces a very complex task. Powerful stochastic optimizers are usually used to determine values and positions of decoupling capacitors on the board. The number of capacitors used has to be determined a priori by the user which brings problems with convergence of the optimization process or can lead to a waste of resources when the noises are to be attenuated to a certain level. In this paper, an approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced. The optimizer works with models having variable dimensions and searches for the optimal one. The approach is tested on two example power circuit boards with various noise attenuation limits and constraints on capacitor positions and values.

PCB Decoupling Optimization With Variable Number of Capacitors

The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

Selection and placement of decoupling capacitors in high speed systems

Great power demands and low-power techniques have increased the requirements on the power delivery network, especially with multiple supply voltages. In this paper, methods for optimizing decoupling capacitor allocation and placement for multiple power nets are presented. Based on a physics-based circuit model extraction for the PCB-PDN structures, a two-level optimization procedure is proposed. First, stackup and potential locations and patterns for power and ground vias are optimized based on design guidelines. In the second step, distribution and allocation of decoupling capacitors are optimized targeting for the system-level PDN performance among multiple supply voltages by an integer linear programming (ILP) algorithm. The physical properties of the decoupling capacitors are described as circuit elements in the equivalent circuit model. Thus, instead of full-wave analysis, only efficient circuit simulations are needed in the optimization process. The proposed optimization methods are applied in a complex system including integrated circuit with multiple supply voltages. Compared to the original unoptimized design, the optimized PDN impedance for the worst designed power nets improved 400% with the same cost of decoupling.

Optimization of power delivery network design for multiple supply voltages

With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

A comparative analysis of jitter estimation techniques

Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods - particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized.

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization

Random jitter (RJ) estimation based on Tail Fit algorithm are generally inaccurate in presence of deterministic components like the presence of sinusoidal jitter (SJ) and duty cycle distortion (DCD). Addition of deterministic jitter changes the standard deviation of the tail region of resulting jitter probability density function. A new methodology for random jitter estimation in presence of sinusoidal jitter and duty cycle distortion is presented. The method involves calculation of mathematical correction factor, which are derived and used to calculate the precise value of random jitter. The proposed methodology is validated by inducing known jitter sources in real channel simulator of ADS from Agilent.

Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm

A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level.

Nitin Kumar Chhabra

Papers

Selection and placement of decoupling capacitors in high speed systems

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization

Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits