Nitin Kumar Chhabra

Abstract: Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network.

Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N P .

Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.

Abstract: With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

Abstract: Great power demands and low-power techniques have increased the requirements on the power delivery network, especially with multiple supply voltages. In this paper, methods for optimizing decoupling capacitor allocation and placement for multiple power nets are presented. Based on a physics-based circuit model extraction for the PCB-PDN structures, a two-level optimization procedure is proposed. First, stackup and potential locations and patterns for power and ground vias are optimized based on design guidelines. In the second step, distribution and allocation of decoupling capacitors are optimized targeting for the system-level PDN performance among multiple supply voltages by an integer linear programming (ILP) algorithm. The physical properties of the decoupling capacitors are described as circuit elements in the equivalent circuit model. Thus, instead of full-wave analysis, only efficient circuit simulations are needed in the optimization process. The proposed optimization methods are applied in a complex system including integrated circuit with multiple supply voltages. Compared to the original unoptimized design, the optimized PDN impedance for the worst designed power nets improved 400% with the same cost of decoupling.

Abstract: The decoupling of modern printed circuit boards introduces a very complex task. Powerful stochastic optimizers are usually used to determine values and positions of decoupling capacitors on the board. The number of capacitors used has to be determined a priori by the user which brings problems with convergence of the optimization process or can lead to a waste of resources when the noises are to be attenuated to a certain level. In this paper, an approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced. The optimizer works with models having variable dimensions and searches for the optimal one. The approach is tested on two example power circuit boards with various noise attenuation limits and constraints on capacitor positions and values.

Abstract: The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

Abstract: An efficient methodology for minimizing core supply noise in Power Delivery Networks is presented. To reduce the power supply noise, an optimal decoupling network is designed by Simulated Annealing. The cumulative impedance of Power Delivery Network is reduced using lesser number of decoupling capacitors compared to placing decoupling capacitors intuitively. The supply noise is minimized according to the requirement of system specifications and the corresponding jitter reduction is reported.