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Author

Nobuki Ueta

Bio: Nobuki Ueta is an academic researcher from Tohoku University. The author has contributed to research in topics: Flip chip & Residual stress. The author has an hindex of 4, co-authored 15 publications receiving 63 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2005
TL;DR: In this paper, the authors discussed the reliability issues such as cracking of LSI chips and deterioration of electronic performance of them caused by mechanical stress and strain in multi-device sub-assembly (MDS) structures.
Abstract: Mechanical reliability issues such as cracking of LSI chips and deterioration of electronic performance of them caused by mechanical stress and strain in multi devices sub-assembly (MDS) structures were discussed analytically and experimentally. Local thermal deformation due to thinning of the LSI chips for mobile application causes large distribution of residual stress from -300 MPa to +150 MPa in the chips. The values of the maximum and the minimum stresses are strong function of the thickness of the LSI chips. In flip chip assembly structures, high tensile stress occurs near the edge of the back surface of the chips and at the edge of small bumps. High compressive stress remains in the center area of the thinner chips because of the reduction of their cross section. Such a wide range of the residual stress causes wide distribution of the shift of electronic performances of devices. Therefore, it is very important to optimize the MDS structures to improve the reliability of products.

13 citations

Proceedings ArticleDOI
01 Jan 2007
TL;DR: In this paper, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps and show that the average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending upon the relative position of bumps between an upper and a bottom interconnection layer.
Abstract: Since mechanical stress and strain change both electronic functions and reliability of LSI chips, it has become strongly important to control the residual stress and strain in them to assure their reliable performance. In this study, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps. The average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps between an upper and a bottom interconnection layer. However, the residual stress of the top chip with a free surface is not affected by the bump alignment in lower interconnection layers. It is very important, therefore, to optimize the thickness of a chip and other structural factors as mentioned above to control not only the average residual stress but also the amplitude of the periodic stress. Finally, the estimated stress distribution in the stacked two chips was proved in detail by the experiment using stress-sensing chips with 2μm long strain gauges consisted of single-crystalline Si.Copyright © 2007 by ASME

12 citations

Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this article, local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length.
Abstract: Local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length. Each strain gauge was made of polycrystalline silicon films deposited on a silicon wafer. The periodic stress distribution was measured at a surface of the sensor chip between two bumps. Five gauges were aligned at a interval of 20-μm between the bumps. When the thickness of the chip was less than 200 μm, the amplitude of the stress increased drastically, as was predicted by a finite element analysis. The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 μm. The amplitude of the stress is a strong function of the thickness of a silicon chip and the intervals of the bumps.Copyright © 2005 by ASME

9 citations

Proceedings ArticleDOI
01 Dec 2006
TL;DR: In this article, a finite element analysis was performed to make clear the quantitative residual stress distribution in stacked chips mounted by flip-chip technology using area-arrayed metallic bumps, and the average residual stress in the stacked two chips varies depending on the distance from a bending neutral axis of the stacked structure, and local residual stress also varies according on the relative position of bumps in an upper connection layer and a bottom connection layer.
Abstract: Since mechanical stress affects both electronic functions and reliability of LSI chips, it has become strongly important to minimize the residual stress in LSI chips This is because the residual stress increases significantly by changing the bonding structure between an LSI chip and a substrate from a wire-bonding structure (WB) to a flip-chip structure (FC) A finite element analysis, therefore, was performed to make clear the quantitative residual stress distribution in stacked chips mounted by flip chip technology using area-arrayed metallic bumps The maximum value of the normal stress on a transistor formation surface of a chip shifts about -200 MPa by changing the assembly structure from WB to FC A periodic distribution with amplitude of about 90 MPa also appears due to the periodic alignment of the metallic bumps Such a change of the residual stress in an LSI chip causes a shift of electronic functions of semiconductor devices in a local area of the chip The important structural factors that determine the distribution of the residual stress are found to be the thickness of a chip, the height of a bump, the width of a bump, the period of the bumps, and the thermal expansion coefficient of underfill material The average residual stress in the stacked two chips varies depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps in an upper connection layer and a bottom connection layer Therefore, it is very important to optimize the thickness of a chip, the position (layout) of bumps, and other structural factors to minimize not only the average residual stress but also the amplitude of the periodic stress distribution Finally, the estimated stress distribution was proved in detail by experiments using stress-sensing chips with 10-mum long gauges

9 citations

Journal ArticleDOI
TL;DR: In this paper, Shin-Saito et al. reported that 2.2 μm of the 2.5 μm was spent on a 2.4 μm-sized container.
Abstract: フリップチップ実装構造内では構造材料であるシリコンや金属バンプ,アンダーフィル,樹脂基板などの弾性率および線膨張係数の相違に起因して局所残留応力分布が発生する。この残留応力の変動振幅が局所的に最大で300 MPaにも達することを,三次元応力解析と試作したゲージ長2 μmのピエゾ抵抗ゲージを搭載したセンサチップを用いて明らかにした。また,Siチップ面内の直交二軸方向の垂直応力の値が変形拘束物となる金属バンプからの距離に依存して大きく変化し,チップ面内のバンプ配置位置に依存して二軸等方的な場が形成される場所と最大で150 MPa以上の差が発生する異方的な場が形成される場所が混在することも明らかにした。

4 citations


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Proceedings ArticleDOI
01 Jun 2010
TL;DR: In this article, a set of low-stress test fixtures were developed to eliminate clamping induced stresses being generated during the sensor resistance measurements, and finite element models of the packaging process were developed and correlated with the test chip data.
Abstract: On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

22 citations

Journal ArticleDOI
TL;DR: In this paper, a piezoresistive CMOS-compatible sensor for measuring the temperature-compensated out-of-plane shear stress components σxz and σyz is analyzed, implemented, and applied.
Abstract: A piezoresistive CMOS-compatible sensor for measuring the temperature-compensated out-of-plane shear stress components σxz and σyz is analyzed, implemented, and applied. The device exploits the shear piezoresistive effect due to vertical (out-of-plane) shear stress components. Possible sensor geometries are discussed and sensitivity considerations based on an affine transformation are presented. A bi-directional, 53 μm × 53 μm-large sensor design measuring two output voltages linearly proportional to the vertical shear stress components σxz and σyz is introduced. The experimental characterization of 17 such structures revealed an offset of the measurement voltage of −1.3 ± 0.6 mV and a linear sensitivity of −320 ± 85 μV/MPa. A variation of the supply voltage from 0 V to 5 V modulates the sensor resistance and voltage-related sensitivity by +6% and −12%, respectively. The geometry dependence of the sensitivity is evaluated using a finite element analysis. Design guidelines are extracted from these simulations. A demonstration of the sensor performance in an application concludes this paper.

18 citations

Proceedings ArticleDOI
26 Apr 2009
TL;DR: In this article, the authors used test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, CBGA components, and flip chip on laminate assemblies.
Abstract: Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

16 citations

Journal ArticleDOI
TL;DR: In this paper, a piezoresistive sensor for measuring the temperature compensated sum ( σ xx ǫ + σ yy )/2ǫ − βσ zz of the three mechanical normal stress components, where σǫ denotes the in-plane normal stress sum, the out-of-planar normal stress, and a numerical factor close to 1 is presented.
Abstract: A piezoresistive sensor for measuring the temperature compensated sum ( σ xx + σ yy )/2 − βσ zz of the three mechanical normal stress components, where σ xx + σ yy , σ zz , and β denote the in-plane normal stress sum, the out-of-plane normal stress, and a numerical factor close to 1 is presented. The device is based on CMOS-compatible diffusions and exploits the piezoresistive effect acting on vertical current components. The sensor signal and resulting possibilities to extract mechanical stress components are analyzed. Experimental results illustrate the influence of design parameters and operating conditions on the sensor performance and are compared to a simple analytical sensor model. A second-order cross-sensitivity to in-plane shear stresses is discussed and determined experimentally. The temperature compensation is demonstrated by a force measurement with a deviation between the numerically expected and the experimentally extracted value smaller than 15% over the temperature range from 10 °C to 60 °C.

16 citations

Proceedings ArticleDOI
30 Jul 2012
TL;DR: In this article, the authors used on-chip piezoresistive stress sensors to quantify die stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment.
Abstract: The increasingly complex packaging used in modern workstations and servers transmits a complicated set of mechanical loads to the microprocessor. Increasing die size, high CTE ceramic substrates, lead free solder joints, and ever increasing power requirements have led to increased die stress levels in packaged microprocessor die. Such stresses can degrade silicon device performance, as well as damage the copper/low-k interconnect layers, and in extreme cases, mechanical failure of the die may occur. In previous work of the authors, on-chip piezoresistive stress sensors have been utilized to quantify stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment. Good correlation has been obtained between the test chip measurements and finite element simulations of the flip chip ceramic ball grid array (FC-CBGA) component assembly process. In the current work, we have extended our past studies on the FC-CBGA microprocessor packaging configuration to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental test chip stress measurements were correlated with finite element simulations of power and thermal cycling events. A sequential modeling approach has been utilized to predict the build-up of die stress. The utilized method incorporates precise thermal histories of the package, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, good correlation has been obtained with the sensor data measured during thermal and power cycling.

15 citations