Nobutaka Kuroki

Bio: Nobutaka Kuroki is an academic researcher from Kobe University. The author has contributed to research in topics: CMOS & Resistor. The author has an hindex of 13, co-authored 64 publications receiving 765 citations.

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

Abstract: This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Abstract: This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.

A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities

Abstract: We have developed a nano-ampere CMOS current reference circuit that is tolerant to threshold voltage variations. This paper describes the circuit and its temperature dependence control technique for ultra-low power LSIs. Because the generated current increases with temperature, we propose a temperature dependence control architecture for a reference current by using the different temperature characteristics of “electron” and “hole” mobilities. Experiment results demonstrated that the circuit can generate a temperature compensated reference current of 9.95 nA and that the temperature dependence of the output reference current can be controlled by using the different temperature dependences of electron and hole mobilities. The temperature dependence controllability was 8.57 pA/˚C·bit and its total current dissipation was 68.1 nA.

A CMOS bandgap and sub-bandgap voltage reference circuits for nanowatt power LSIs

Abstract: This paper proposes CMOS bandgap reference (BGR) and sub-BGR circuits without resistors for nanowatt power LSIs. The BGR circuit consists of a nano-ampere current reference, a bipolar transistor, and a proportional to absolute temperature (PTAT) voltage generator. The PTAT voltage generator consists of source-coupled differential pairs and generates a positive temperature dependent voltage. The PTAT voltage generator compensates for negative temperature dependence of a base-emitter voltage in a PNP bipolar transistor. The circuit generates a bandgap voltage of silicon. The sub-BGR circuit uses a voltage divider to generate low-voltage sub-bandgap reference. Experimental results demonstrated that the BGR and sub-BGR circuits can generate a 1.18-V and 553-mV reference voltages, respectively. The power dissipation of the BGR and sub-BGR circuits were 108-nW and 110-nW, respectively.

Edge-directed prediction for lossless compression of natural images

Abstract: This paper sheds light on the least-square (LS)-based adaptive prediction schemes for lossless compression of natural images. Our analysis shows that the superiority of the LS-based adaptation is due to its edge-directed property, which enables the predictor to adapt reasonably well from smooth regions to edge areas. Recognizing that LS-based adaptation improves the prediction mainly around the edge areas, we propose a novel approach to reduce its computational complexity with negligible performance sacrifice. The lossless image coder built upon the new prediction scheme has achieved noticeably better performance than the state-of-the-art coder CALIC with moderately increased computational complexity.

Point cloud attribute compression with graph transform

Abstract: Compressing attributes on 3D point clouds such as colors or normal directions has been a challenging problem, since these attribute signals are unstructured. In this paper, we propose to compress such attributes with graph transform. We construct graphs on small neighborhoods of the point cloud by connecting nearby points, and treat the attributes as signals over the graph. The graph transform, which is equivalent to Karhunen-Loeve Transform on such graphs, is then adopted to decorrelate the signal. Experimental results on a number of point clouds representing human upper bodies demonstrate that our method is much more efficient than traditional schemes such as octree-based methods.

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

Abstract: This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

Image compression with neural networks } A survey

Abstract: Apart from the existing technology on image compression represented by series of JPEG, MPEG and H.26x standards, new technology such as neural networks and genetic algorithms are being developed to explore the future of image coding. Successful applications of neural networks to vector quantization have now become well established, and other aspects of neural network involvement in this area are stepping up to play significant roles in assisting with those traditional technologies. This paper presents an extensive survey on the development of neural networks for image compression which covers three categories: direct image compression by neural networks; neural network implementation of existing techniques, and neural network based technology which provide improvement over traditional algorithms.

A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems

Abstract: This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade-off between diode current between n-well and p-sub and process variation. Prototype chips are fabricated in a 0.18- $\mu \text{m}$ CMOS process. Measurement results from three wafers show $3\sigma $ inaccuracy of ±1.0% from 0 °C to 100 °C after a single room-temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.