Nuno Paulino

Bio: Nuno Paulino is an academic researcher from Universidade Nova de Lisboa. The author has contributed to research in topics: CMOS & Switched capacitor. The author has an hindex of 16, co-authored 127 publications receiving 945 citations. Previous affiliations of Nuno Paulino include University of Lisbon & Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa.

Modem having a programmable universal data access arrangement

Abstract: A modem utilizing a DAA having line side circuitry including a telephone network interface and system side circuitry including a host system interface, the line side circuitry and the system side circuitry being separated by a high voltage isolation barrier. A CODEC is provided in the line side circuitry, such that encoded information generated by the CODEC, as well as information for decoding by the CODEC, are communicated across the high voltage isolation barrier. These communications are accomplished in a digital manner. In an alternate embodiment of the invention, the line side circuitry of the modem further includes programmable detection and measurement circuitry that is programmable to measure electrical characteristics (e.g., tip/ring voltage and loop current) of the telephone line interface connection and is capable of corresponding adjustments to enable compliance with applicable regulations. The system is software programmable via control signals sent across the high voltage isolation barrier to establish electrical parameters corresponding to a specific country where the equipment may be used.

A 0.9V /spl Delta//spl Sigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique

Abstract: A 2nd-order DeltaSigma ADC implemented in 0.18mum CMOS occupies 0.06mm2 and dissipates 0.2mW from a 0.9V supply. It achieves 80dB SNDR and 83dB DR over a 10kHz BW employing a single-phase technique to reach such performance. An amplifier-sharing scheme is proposed to improve power and area efficiency

An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

Abstract: This paper presents an improved low-voltage low-power CMOS comparator suitable for high-speed pipeline ADCs. Simulated results of the proposed circuit in a 0.35 /spl mu/m standard CMOS technology operating at supply voltages within the range of 1.0-1.5 V show that this comparator achieves low offset, reduced kickback noise, high mean-time to failure and exhibits low-power dissipation at very high-speed operation.

Design methodology for optimization of analog building blocks using genetic algorithms

Abstract: This paper presents an equation-based design methodology for optimization of analog building blocks using genetic algorithms The proposed methodology uses the analytical equations that describe the circuit's behavior as a function of the design parameters such as the transistor dimensions and/or the passive component values These parameters are then subject to an optimization process, using genetic algorithms, in order to fit the circuit performance into the desired specifications This design methodology is suited for fast redesigns of analog blocks into new technologies

Design Of Analog Cmos Integrated Circuits

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Micropower energy harvesting

Abstract: More than a decade of research in the field of thermal, motion, vibration and electromagnetic radiation energy harvesting has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC-DC conversion are becoming able to efficiently convert the power from these energy harvesters. This paper summarizes recent energy harvesting results and their power management circuits.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

Kickback noise reduction techniques for CMOS latched comparators

Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.