There has been a great deal of material in the area of discrete-time transforms that has been published in recent years. This book does an excellent job of presenting important aspects of such material in a clear manner. The book has 11 chapters and a very useful appendix. Seven of these chapters are essentially devoted to the Fourier series/transform, discrete Fourier transform, fast Fourier transform (FFT), and applications of the FFT in the area of spectral estimation. Chapters 8 through 10 deal with many other discrete-time transforms and algorithms to compute them. Of these transforms, the KarhunenLoeve, the discrete cosine, and the Walsh-Hadamard transform are perhaps the most well-known. A lucid discussion of number theoretic transforms i5 presented in Chapter 11. This reviewer feels that the authors have done a fine job of compiling the pertinent material and presenting it in a concise and clear manner. There are a number of problems at the end of each chapter, an appreciable number of which are challenging. The authors have included a comprehensive set of references at the end of the book. In brief, this book is a valuable contribution to the general areas of signal processing and communications. It can be used for a graduate level course in perhaps two ways. One would be to cover the first seven chapters in great detail. The other would be to cover the whole book by focussing on different topics in a selective manner. This book  by  Elliott  and Rao  is extremely  useful to researchers/engineers who are working  in the areas of signal processing and communications. It i s also an excellent reference book, and hence a valuable addition to one’s library

http://ieeexplore.ieee.org/iel5/5/31347/01457444.pdf

Multirate digital signal processing

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffer from a problem not seen in discrete-time (DT) designs, that of excess loop delay: nonzero delay between the quantizer clock edge and the time when a change in output bit is seen at the feedback point in the modulator. This paper analytically shows how such delay affects the equivalence between the CT modulator loop filter and its DT counterpart. The effect of this delay on modulator dynamic range is studied through simulation for the standard double-integration (low pass) CT modulator and its equivalent fourth-order f/sub s//4 band pass circuit. For the first time, the results are extended to higher order low-pass and bandpass designs, as well as multibit designs. Methods for alleviating the performance loss caused by excess loop delay are also discussed.

Excess loop delay in continuous-time delta-sigma modulators

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

/pdf/continuous-time-delta-sigma-a-d-converters-for-high-speed-3dt0vh25bn.pdf

Continuous-Time Delta-Sigma A/D Converters for High Speed Applications

The discrete-time /spl Delta//spl Sigma/ modulator is transformed to the continuous-time /spl Delta//spl Sigma/ modulator. For either nonreturn to-zero or return to-zero feedback, the loop transfer functions of the continuous-time and discrete-time modulators can be made exactly equivalent. Hence, a stable discrete-time /spl Delta//spl Sigma/ modulator is mapped to a stable continuous-time /spl Delta//spl Sigma/ modulator having the same SNR. The anti-alias (image rejection) properties of the continuous-time modulator are described. Experimental results for a tunable 40 MHz-70 MHz continuous-time Gm-C modulator are shown to verify the theory. A master-slave tuning scheme is developed to tune the Gm-C /spl Delta//spl Sigma/ loop filter.

Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass /spl Delta//spl Sigma/ modulator

In this paper, we show that excess loop delay seriously degrades the performance of continuous-time delta-sigma modulators (/spl Delta//spl Sigma/M's). It is then demonstrated in theory that the effect can be alleviated by tuning the feedback digital-to-analog converter pulse-shaping coefficients.

Excess loop delay effects in continuous-time delta-sigma modulators and the compensation solution

Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment.

/pdf/modeling-of-switched-capacitor-delta-sigma-modulators-in-h8h1qj15x4.pdf

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

A new technique for designing an LC bandpass delta-sigma modulator is presented. This method is based on pulse shaping of a DAC output signal such that one can realize a desired (arbitrary) loop transfer function. Especially for higher-order modulators where extra LC sections are added, sufficient number of parameters are provided in the feedback loop. It is shown that by creating more degrees of freedom one can achieve the maximum SNR in a given modulator order without constraining the noise transfer function of the modulator.

/pdf/a-multi-feedback-design-for-lc-bandpass-delta-sigma-fec6pq5eqy.pdf

Omid Shoaei

Papers

Continuous-Time Delta-Sigma A/D Converters for High Speed Applications

Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass /spl Delta//spl Sigma/ modulator

Excess loop delay effects in continuous-time delta-sigma modulators and the compensation solution

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

A multi-feedback design for LC bandpass delta-sigma modulators