O
Oskar Mencer
Researcher at Imperial College London
Publications - 109
Citations - 3124
Oskar Mencer is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 28, co-authored 108 publications receiving 3009 citations. Previous affiliations of Oskar Mencer include Stanford University & University of Western Australia.
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Journal ArticleDOI
Reconfigurable computing: architectures and design methods
Tim Todman,George A. Constantinides,Steven J. E. Wilton,Oskar Mencer,Wayne Luk,Peter Y. K. Cheung +5 more
TL;DR: It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
Journal ArticleDOI
Accuracy-Guaranteed Bit-Width Optimization
TL;DR: An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented and is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA.
Journal ArticleDOI
Seeking solutions in configurable computing
William H. Mangione-Smith,Brad Hutchings,David L. Andrews,André DeHon,Carl Ebeling,Reiner W. Hartenstein,Oskar Mencer,J. Morris,Krishna V. Palem,Viktor K. Prasanna,H.A.E. Spaanenburg +10 more
TL;DR: The configurable computing community should focus on refining the emerging architectures, producing more effective software/hardware APIs, better tools for application development that incorporate the models of hardware reconfiguration, and effective benchmarking strategies.
Proceedings ArticleDOI
PAM-Blox: high performance FPGA design for adaptive computing
TL;DR: PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC, intended to be part of an open library that allows design sharing between members of the adaptive computing community.
Proceedings ArticleDOI
Unifying bit-width optimisation for fixed-point and floating-point designs
TL;DR: A method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs and is implemented in the BitSize tool targeting reconfigurable architectures, which takes user-defined constraints to direct the optimisation procedure.