Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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Coarse-Grained Reconfigurable Array Architectures

Advanced telecommunication applications require more and more flexibility. Static and run-time configuration mechanisms, as well as plug-in computing units are two solutions to solve this issue. In this paper, we propose an open architec- ture, dedicated to complex data-flow applications, fulfilling these requirements thanks to a distributed configuration scheme and a standard interface for data flow computing units. Based on this architecture, an open platform demonstrator has been designed. Simulation results on a 3GPP/LTE application are presented, showing a reconfiguration time overhead of only 2.6%.

An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

The continuously increasing number of communication standards to be supported in nomadic devices combined with the fast ramping design cost in deep submicron technologies claim for highly reusable and flexible programmable solutions. Software defined radio (SDR) aims at providing such solutions in radio baseband architectures. Great advances were recently booked in handset-targeted SDR, covering most of the baseband processing with satisfactory performance and energy efficiency. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of high throughput SDR solutions and let to dedicated hardware accelerators. The currently growing number of advanced FEC options claims however for flexibility there too. This paper presents the first application-specific instruction programmable architecture addressing in a unified way the emerging turbo- and LPDC coding requirements of 3GPP-LTE, IEEE802.11n, IEEE802.16(e) and DVB-S2/T2. The proposal shows a throughput from 0.07 to 1.25 Mbps/MHz with efficiencies round 0.32 nJ/bit/iter in turbo mode and round 0.085 nJ/bit/iter in LDPC mode. The area is lower than the cumulated area of dedicated turbo and LDPC solution.

A unified instruction set programmable architecture for multi-standard advanced forward error correction

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

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State of the art baseband DSP platforms for Software Defined Radio: A survey

We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map applications to a 90-nm field-programmable gate array (FPGA), giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90-nm technology, and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial very long instruction word digital signal processor processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications.

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BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

The software-defined radio (SDR) concept aims to enabling cost-effective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. Coarse-grained array (CGA) processors are strong candidates to undertake both high performance and low power. The design of a candidate hybrid CGA-SEVID processor for an SDR baseband platform is presented. The processor, designed in TSMC 90 G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400 MHz in worst case conditions and consumes maximally 310 mW active and 25 mW leakage power (typical conditions) when delivering up to 25,6 GOPS (16-bit). The mapping of a 20 MHz 2times2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100 Mbps+ throughput with an average consumption of 220 mW.

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A coarse-grained array based baseband processor for 100Mbps+ software defined radio

A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit.

Time stamp generation

This paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power-efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank conflicts among the single-ported banks, and to spread long bursts of conflicting accesses to the same bank over time. Bank address rotation is used to spread long bursts of conflicting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank conflicts can be reduced to below 2% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13%. This is achieved with little energy and area overhead, and without any bank-aware compiler support.

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An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

The power consumption is a key aspect when designing a handheld device. Even when cycle accurate instruction set simulators for the ASIPs used in SDRs are existing to evaluate the performance of given mapping, the power consumption is evaluated only in the later phase during gate-level simulation. In this paper we propose an automatic way how to obtain dynamic energy consumption per opcode activation of an ASIP baseband-processor of our SDR platform. We use the results obtained for time-space energy consumption modeling of dynamic reconfigurable CGA processor datapath at the instruction set simulator level that we demonstrate on WLAN 2×2 40MHz application. The results allow us to propose important application and architectural changes for our ASIP.

Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications

Correction of offset applied to time stamps generated in response to an event is described. Each time stamp comprises a coarse count and a fine count. The fine count may have an offset, which if not corrected properly, creates a rollover providing an error in the digital output corresponding to the time stamp. Rollover is prevented by knowing, for each event to be time stamped, the half of the clock period in which the event occurred. A circuit (1000) can be utilised for determining a flag relating to the event, the flag being indicative of the half of the clock period in which the event occurred. The circuit (1000) comprises an analogue front end (1010) associated with every channel to be monitored, and a digital processor (1025, 1060, 1080, 1085, 1090) that processes event signals (1015) from each analogue front end (1010) to determine the time stamp for each event occurring in a multi-channel system. A method of operation of the circuit (1000) is also disclosed.

Osman Allam

Papers

A coarse-grained array based baseband processor for 100Mbps+ software defined radio

Time stamp generation

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications

Improvements in or relating to time stamp generation