O
Osvaldo Jorge Lopez
Researcher at Texas Instruments
Publications - 38
Citations - 345
Osvaldo Jorge Lopez is an academic researcher from Texas Instruments. The author has contributed to research in topics: Terminal (electronics) & Transistor. The author has an hindex of 11, co-authored 38 publications receiving 345 citations.
Papers
More filters
Patent
Semiconductor device package and method of assembly thereof
TL;DR: A semiconductor die package includes an assembly including a die, a clip structure attached to an upper surface of the die, and a heat sink attached to the clip structure.
Patent
Integrating multi-output power converters having vertically stacked semiconductor chips
Marie Denison,Brian Carpenter,Osvaldo Jorge Lopez,Juan Alejandro Herbsommer,Jonathan A. Noquil +4 more
TL;DR: In this paper, a multi-output converter with a chip pad as ground terminal and a plurality of leads including the electrical input and output terminals is presented. But the chip pad is not attached to the output lead.
Patent
Wirebond-less semiconductor package
TL;DR: A wirebondless packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the die having a bottom major surface and a top major surface, and a conductive clip system disposed over the top major surfaces, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/On contacts as mentioned in this paper.
Patent
Mosfet with gate pull-down
TL;DR: A pull-down MOSFET (110) is coupled between a drain and gate of a main switch transistor (102) in a switching type DC-to-DC power converter as mentioned in this paper.
Patent
Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance
TL;DR: In this paper, a power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the source terminal attached to