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Author

P. Allen

Bio: P. Allen is an academic researcher. The author has contributed to research in topics: Phase-locked loop & Direct digital synthesizer. The author has an hindex of 1, co-authored 1 publications receiving 16 citations.

Papers
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Proceedings ArticleDOI
30 May 1999
TL;DR: Feedforward compensation combined with feedback regulation is utilized to achieve a high switching speed and a low phase noise for narrow bandwidth digital phase-locked loop (DPLL).
Abstract: Traditional feedback-controlled digital phase-locked loop (DPLL) based frequency synthesizers suffer from the tradeoff between output phase noise and dynamic response of the loop. In this paper, feedforward compensation combined with feedback regulation is utilized to achieve a high switching speed and a low phase noise for narrow bandwidth digital phase-locked loop (DPLL). Simulation results demonstrate the efficacy of this method.

16 citations


Cited by
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Journal ArticleDOI
TL;DR: A novel method of estimating gain of a digitally-controlled oscillator (DCO) for wireless RF applications is proposed and demonstrated by executing the calculation algorithm just in-time at the beginning of every packet, which enables the employment of sophisticated and fully-digital frequency synthesizers capable of compensating for analog nonidealities.
Abstract: A novel method of estimating gain of a digitally-controlled oscillator (DCO) for wireless RF applications is proposed and demonstrated. By executing the calculation algorithm just-in-time at the beginning of every packet, the DCO gain can be conveniently tracked and compensated. Precise and timely knowledge of the DCO gain makes possible various predictive operations of a frequency synthesizer such as the presented digital direct frequency modulation using a hybrid of predictive/closed modulation method. This enables the employment of sophisticated and fully-digital frequency synthesizers capable of compensating for analog nonidealities. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process. The presented ideas have been incorporated in a fully-compliant Bluetooth transceiver.

68 citations

Journal ArticleDOI
TL;DR: A fast lock digital phase-locked-loop frequency synthesizer for wireless applications with small area and digitally selectable frequency resolution and a fully digital solution to reducing the phase lock time is reported.
Abstract: A fast lock digital phase-locked-loop (PLL) frequency synthesizer for wireless applications is reported. The main advantages of the architecture include small area and digitally selectable frequency resolution. Also, a fully digital solution to reducing the phase lock time is introduced. This work is also supported by a nonlinear analytical analysis of the locking mechanism for PLLs.

32 citations

Proceedings ArticleDOI
27 Jun 2012
TL;DR: This paper outlines an identification scheme that tunes parameters for a large class of periodic motions, and requires only a small number of identification experiments prior to flight, and shows the effectiveness of this approach by performing a sequence of periodic movements on real quadrocopters using the tuned parameters obtained by the reduced identification.
Abstract: This paper presents an approach for precisely tracking periodic trajectories with a quadrocopter. In order to improve temporal and spatial tracking performance, we propose a feed-forward strategy that adapts the motion parameters sent to the vehicle controller. The motion parameters are either adjusted on the fly or, in order to avoid initial transients, identified prior to the flight performance. We outline an identification scheme that tunes parameters for a large class of periodic motions, and requires only a small number of identification experiments prior to flight. This reduced identification is based on analysis and experiments showing that the quadrocopter's closed-loop dynamics can be approximated by three directionally decoupled linear systems. We show the effectiveness of this approach by performing a sequence of periodic motions on real quadrocopters using the tuned parameters obtained by the reduced identification.

28 citations

Journal ArticleDOI
TL;DR: A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper and the measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz.
Abstract: A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. To verify the proposed algorithm and architecture, the ADPLL design is implemented by SMIC 0.18-μm 1P6M CMOS technology. The core size of the ADPLL is 582.2 μm * 343 μm. The frequency range of the ADPLL is from 4 to 416 MHz. The measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz. The corresponding power consumption is 11.394 mW.

26 citations

Patent
02 Oct 2001
TL;DR: In this paper, a time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of a lower frequency timing signal.
Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

21 citations