This review covers important advances in recent years in the physics of thin-film ferroelectric oxides, the strongest emphasis being on those aspects particular to ferroelectrics in thin-film form. The authors introduce the current state of development in the application of ferroelectric thin films for electronic devices and discuss the physics relevant for the performance and failure of these devices. Following this the review covers the enormous progress that has been made in the first-principles computational approach to understanding ferroelectrics. The authors then discuss in detail the important role that strain plays in determining the properties of epitaxial thin ferroelectric films. Finally, this review ends with a look at the emerging possibilities for nanoscale ferroelectrics, with particular emphasis on ferroelectrics in nonconventional nanoscale geometries.

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Physics of thin-film ferroelectric oxides

Degradation of silicon dioxide films is shown to occur primarily near interfaces with contacting metals or semiconductors. This deterioration is shown to be accountable through two mechanisms triggered by electron heating in the oxide conduction band. These mechanisms are trap creation and band‐gap ionization by carriers with energies exceeding 2 and 9 eV with respect to the bottom of the oxide conduction band, respectively. The relationship of band‐gap ionization to defect production and subsequent degradation is emphasized. The dependence of the generated sites on electric field, oxide thickness, temperature, voltage polarity, and processing for each mechanism is discussed. A procedure for separating and studying these two generation modes is also discussed. A unified model from simple kinetic relationships is developed and compared to the experimental results. Destructive breakdown of the oxide is shown to be correlated with ‘‘effective’’ interface softening due to the total defect generation caused by both mechanisms.

Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon

The utilization of organic devices as pressure-sensing elements in artificial intelligence and healthcare applications represents a fascinating opportunity for the next-generation electronic products. To satisfy the critical requirements of these promising applications, the low-cost construction of large-area ultra-sensitive organic pressure devices with outstanding flexibility is highly desired. Here we present flexible suspended gate organic thin-film transistors (SGOTFTs) as a model platform that enables ultra-sensitive pressure detection. More importantly, the unique device geometry of SGOTFTs allows the fine-tuning of their sensitivity by the suspended gate. An unprecedented sensitivity of 192 kPa(-1), a low limit-of-detection pressure of <0.5 Pa and a short response time of 10 ms were successfully realized, allowing the real-time detection of acoustic waves. These excellent sensing properties of SGOTFTs, together with their advantages of facile large-area fabrication and versatility in detecting various pressure signals, make SGOTFTs a powerful strategy for spatial pressure mapping in practical applications.

/pdf/flexible-suspended-gate-organic-thin-film-transistors-for-2jmzct5u8y.pdf

Flexible suspended gate organic thin-film transistors for ultra-sensitive pressure detection

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.

A capacitor-less 1T-DRAM cell

A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept should allow the manufacture of low cost DRAMs and eDRAMs for 100 and sub 100 nm generations.

A SOI capacitor-less 1T-DRAM concept

A data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed. Each data storage cell (10) has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit (16), writing circuits (18) and a refreshing circuit (22) apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Data storage device and refreshing method for use with such device

In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices.

P. Fazan

Papers

A capacitor-less 1T-DRAM cell

A SOI capacitor-less 1T-DRAM concept

Data storage device and refreshing method for use with such device

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

Principles of transient charge pumping on partially depleted SOI MOSFETs