P
P. Iyer
Researcher at Intel
Publications - 2
Citations - 742
P. Iyer is an academic researcher from Intel. The author has contributed to research in topics: Register file & Network on a chip. The author has an hindex of 2, co-authored 2 publications receiving 733 citations.
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Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Proceedings ArticleDOI
Testing high-speed IO links using on-die circuitry
TL;DR: A novel technique to enable characterization of high-speed IO links and transceivers without the use of special external test equipment is described and results show that the system can successfully test the system and capture the behavior of the transceiver and link.