In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

In this work, we are using voltage scaling to make the counter design as an energy efficient design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL and CMOS logic families. In addition to performing the counting function, it can be cleared or loaded in parallel. It has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs. Out of which in case of clock the maximum power dissipation is in range of 12.126W to 35.056W at which is in case of 1THz when measured at different voltage levels where as in case of IOs the maximum power dissipation is in range of 20.636W to 25.031W. Which is again in case of 1THz when measured at different voltage levels. There is not much significant change in case of signal and leakage power at different voltage levels. The maximum total power dissipation is in range of 33.887W to 67.986W at frequency of 1THz when operated at different voltages. Also there can be 94.45% to 99.61% reduction in total power dissipation if we operate on frequency of 1MHz instead of frequency of 1THz at different Voltage levels.

Energy Efficient Counter Design Using Voltage Scaling on FPGA

Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

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SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Tuberculosis (TB) remains major cause of morbidity and mortality due to any one of infectious agent worldwide. In low income countries, Ziehl-Neelsen sputum smear microscopy is the only cost-effective tool for diagnosis and monitoring of patients on treatment. In order to have efficient AFB microscopy centers, it is imperative to have continuous refresher training for laboratory professionals and strong External Quality Assessment (EQA) system). However, very little data exists as to the effect of in-service training on performance of laboratory personnel in Ethiopia. The objective of this study was to investigate the role of AFB microscopy refresher training on the performance of laboratory professionals. A cross-sectional retrospective study was conducted to appraise theoretical and practical performance of laboratory professionals before and after AFB microscopy training. Theoretical assessment was based on standard questions while practical assessment was based on smear reading of 10 standard slides. Data on eight rounds of a five days training at Adama regional laboratory on AFB microscopy in 2009 was obtained and analyzed using SPSS 16.0 statistical software. The pre-training mean score of the theoretical knowledge and practical skills were 61.8% and 75.7%, respectively. The post training mean scores were 84.2% and 89.2% for theoretical knowledge and practical skills, respectively. The increase in mean score of both theoretical and practical assessment was statistically significant (p < 0.0001). Post training mean score of theoretical knowledge was higher among diploma holders trainees than the BSc degree counter parts (p = 0.001). The mean scores on practice before and after training was dependent on participation in previous AFB microscopy trainings (p < 0.0001). Proportions of trainees with both major and minor errors were found to decrease after they were trained. Trainees who have had previous training were found to commit less errors than those who were not participated in previous training (p < 0.0001). Training has improved theoretical and practical performance of laboratory professionals. Pre-placement and continuous training irrespective of lab professionals qualification and service year and sustainable EQA are highly recommended to ensure quality of AFB microscopy service.

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The role of AFB microscopy training in improving the performance of laboratory professionals: analysis of pre and post training evaluation scores

In this work, we are using voltage scaling and frequency scaling In voltage scaling, voltage is scaled from 3V to 1V, where intermediate values are 25V, 2V, 18V and 15V In frequency scaling, frequency is scaled from 1 MHz to 1 THz, where intermediate values are 10 MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz When we scale down device operating frequencies from 1THz to 1GHz, there is 729% reduction in power dissipation on Virtex-6 FPGA When we scale down device operating frequencies from 1THz to 1GHz, there is 9875% reduction in power dissipation on Virtex-4 FPGA When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 8223%, 9683%, 9845% and 99% reduction in power dissipation respectively on Virtex-6 FPGA on 10MHz device operating frequency When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 7442%, 9267%, 9471% and 9766% reduction in power dissipation respectively on Virtex-6 FPGA on 1THz device operating frequency

http://ieeexplore.ieee.org/iel7/7109473/7115730/07115855.pdf

Energy efficient flip flop design using voltage scaling on FPGA

In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.

Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards

In this paper, we are implementing green Integrator. Digital integrator is an analog to digital converter. Which is designed in Xilinx ISE14.6 using various IO standard of SSTL in 28nm Kintex-7 FPGA. We are comparing different IO standard of SSTL to get minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. We are using different classes of SSTL in this entire paper and analyzed that when integrator device operating frequency is 1THz then there is 76.65% reduction in IO power of SSTL135_DCI as compare to SSTL135_R I/O Standard on Kintex-7 FPGA. Likewise at 2GHz, our integrator IO power reduction is 70.14% of SSTL12 with respect to SSTL12_DCI of IO standard using kintex-7 FPGA. When we see the dynamic clock power variations it's almost same in every frequency i.e. 15%. Similarly when we operate parallel integrator at 200 GHz via kintex-7, there is 28.12% decrease in signal power of SSTL135_R with respect to SSTL135_DCI Standard. The Leakage power of integrator is decrease 16.21% of SSTL135_DCI as compared to SSTL135_R at 1 THz device operating frequency.

Simulation of SSTL IO standard based power optimized parallel integrator design on FPGA

The credibility, success, and sustainability of the Revised National Tuberculosis Control Programme (RNTCP) depend on the strength of the laboratory network. Sputum Smear Microscopy has been the corner stone of Tuberculosis (TB) diagnosis and disease monitoring in RNTCP. To achieve and maintain the national objectives of 85% treatment cure rate among new Pulmonary Sputum Positive TB cases, and to achieve and maintain detection of at least 70% of such cases, quality assurance of Sputum Smear Microscopy is most immediate need. Quality Assurance (QA) system enhances the performance of the laboratory by validating methods with Internal Quality Control (IQC) and External Quality Assessment schemes (EQA). IQC & EQA identifies inappropriate procedures, out-of-date reagents, uncontrolled instrumentation, and /or training needs of incompetent or untrained staff. EQA improves sputum smear microscopy performance by retrospective analysis of the laboratory’s testing procedure. by comparison with other testing laboratories and a reference laboratory. 

The main focus of revised EQA programme, in India is given to: (a) the On-site evaluation (OSE) of laboratories in a periodic fashion, (b) monthly Random blinded Rechecking (RBRC) of the routine Designated Microscopy Centre (DMC) slides using statistically valid sampling procedure- Lot Quality Assurance Sampling (LQAS)- for rechecking programme, (c) proficiency testing of supervisors with panel testing, and (d) strengthening the state level laboratories (labs) for evaluating the peripheral labs. The revised EQA is being implemented in a phased manner in the country. EQA-teams (one microbiologist and two senior lab technicians) of majority of state level labs have been trained. Specific operational and technical problems are continuously identified and addressed with corrective measures. An efficient EQA system would install confidence in RNTCP diagnostic algorithm by identifying and correcting the systematic operational and technical errors in the laboratories.

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External quality assessment system for sputum smear microscopy in india : operational and technical implementation aspects

Laboratory Diagnosis of Acid-fast bacilli by Sputum Smear Microscopy is an important component of Revised National Tuberculosis control Program (RNTCP). An effective External Quality Assessment (EQA) network would install confidence in RNTCP diagnostic algorithm. RNTCP has implemented specific programs such as Public Private Mix (PPM) involving the participation of Private Medical practitioners, Medical colleges, Non-Governmental organizations, and corporate hospitals. To assess the awareness of EQA structure and functional implementation aspects and for Drug resistance surveillance, a written survey was conducted. Postgraduate medical students attending Indian Association of Medical Microbiologists (IAMM) IX annual meeting of Karnataka Chapter participated in this study. A methodology of pre-test, structuredlecture and discussion, followed by a post-test that incorporated all the aspects of revised EQA guidelines for smear microscopy and finer aspects of drug sensitivity testing (DST) was adopted. The average performance of participants regarding questions on ‘Methodology for Sputum smear- ZN staining and result grading as per RNTCP’ and questions on ‘mycobacterial culture and Drug resistance surveillance’ were 44.5% and 30% for pre-test, that changed to 88.2% and 70.9%, respectively in the post-test assessment. The average performance for questions on ‘Structural organization of EQA network’ and questions on ‘Functional organization of EQA network’ between pre and post test was from 22.7% to 54.4%, and 36.6% to 69.9%, respectively. The methodology used, and the questionnaire developed for this purpose could be used as an instrument for largescale studies of this nature before RNTCP makes imperative policy decisions regarding EQA network in the private sector in India.

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AWARENESS OF 'EXTERNAL QUALITY ASSESSMENT' NETWORK FOR AFB SPUTUM SMEAR MICROSCOPY & DRUG SENSITIVITY TESTING FOR M.tuberculosis AMONG POST-GRADUATE MEDICAL STUDENTS

The paper reports the qualitative and quantitative assessment of the NTI OSE check- lists for the years 2005 and 2006 of ten state- level Intermediate Reference laboratories (IRLs) to establish effective supervision for quality of sputum smear microscopy. The assessment also indicates the effectiveness of NTI-OSEs. Quality related problems were identified, causes explored and solutions provided for establishing quality sputum microscopy network. NRL OSE reports, IRL OSE reports, RBRC records and action-taken-reports formed the material for assessment.

/pdf/qualitative-quantitative-assessment-of-ten-intermediate-5f1iqgyx2o.pdf

Qualitative & quantitative assessment of ten Intermediate Reference Laboratories for quality of sputum smear microscopy based on RNTCP on-site evaluation

P Kumar

Papers

Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards

Simulation of SSTL IO standard based power optimized parallel integrator design on FPGA

External quality assessment system for sputum smear microscopy in india : operational and technical implementation aspects

AWARENESS OF 'EXTERNAL QUALITY ASSESSMENT' NETWORK FOR AFB SPUTUM SMEAR MICROSCOPY & DRUG SENSITIVITY TESTING FOR M.tuberculosis AMONG POST-GRADUATE MEDICAL STUDENTS

Qualitative & quantitative assessment of ten Intermediate Reference Laboratories for quality of sputum smear microscopy based on RNTCP on-site evaluation