Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems-an NSF Engineering Research Center.

Three-dimensional packaging for power semiconductor devices and modules

The recent developments in power semiconductor devices and increasing demands on reliability as well as on operation performance require innovative package technologies. Such a novel package technique based on a Planar Interconnect Technology (SiPLIT(r)) for power modules is introduced in this work. This package features thick Cu interconnects on a high-reliable insulating film for power semiconductor chip top contacts. Due to the conductor structure and contact technology, on-resistance and stray inductances are very low compared to state-of-the-art Al wire bonds. In addition, large area contacting improves the power cycling capability and surge current robustness significantly. These remarkable properties have been verified on several prototype modules where the manufacturing process has also been optimised in terms of cost-effectiveness, system integration and maturity for series production.

Planar Interconnect Technology for Power Module System Integration

iii inductances on the MOSFET’s switching waveforms. A small-signal model is then developed to explain the parasitic ringing in the frequency domain. From this angle, the ringing mechanism can be understood more easily and deeply. With the use of this model, the effects of DC decoupling capacitors in suppressing the ringing can be further explained in a more straightforward way than the traditional time-domain analysis. A rule of thumb regarding the capacitance selection is also derived. A Power Electronics Building Block (PEBB) module is then developed with discrete SiC MOSFETs. Integrating the power stage together with the peripheral functions such as gate drive and protection, the PEBB concept allows the converter to be built quickly and reliably by simply connecting several PEBB modules. The high-speed gate drive and power stage layout designs are presented to enable fast and safe switching of the SiC MOSFET. Based on the PEBB platform, the state-of-the-art Si and SiC power MOSFETs are also compared in the device characteristics, temperature influences, and loss distributions in a high-frequency converter, so that special design considerations can be concluded for the SiC MOSFET. Towards high-temperature, high-frequency and high-power operations, integrated wire-bond phase-leg modules are also developed with SiC MOSFET bare dice. Hightemperature packaging materials are carefully selected based on an extensive literature survey. The design considerations of improved substrate layout, laminated bus bars, and embedded decoupling capacitors are all discussed in detail, and are verified through a modeling and simulation approach in the design stage. The 200 °C, 100 kHz continuous operation is demonstrated on the fabricated module. Through the comparison with a commercial SiC phase-leg module designed in the traditional way, it is also shown that

Electrical Integration of SiC Power Devices for High-Power-Density Applications

This paper presents the feasibility of highly reliable and repeatable copper–tin transient liquid phase (Cu–Sn TLP) bonding as applied to die attachment in high temperature operational power modules. Electrified vehicles are attracting particular interest as eco-friendly vehicles, but their power modules are challenged because of increasing power densities which lead to high temperatures. Such high temperature operation addresses the importance of advanced bonding technology that is highly reliable (for high temperature operation) and repeatable (for fabrication of advanced structures). Cu–Sn TLP bonding is employed herein because of its high remelting temperature and desirable thermal and electrical conductivities. The bonding starts with a stack of Cu–Sn–Cu metal layers that eventually transforms to Cu–Sn alloys. As the alloys have melting temperatures (Cu3Sn: > 600 °C, Cu6Sn5: > 400 °C) significantly higher than the process temperature, the process can be repeated without damaging previously bonded layers. A Cu–Sn TLP bonding process was developed using thin Sn metal sheets inserted between copper layers on silicon die and direct bonded copper substrates, emulating the process used to construct automotive power modules. Bond quality is characterized using (1) proof-of-concept fabrication, (2) material identification using scanning electron microscopy and energy-dispersive x-ray spectroscopy analysis, and (3) optical analysis using optical microscopy and scanning acoustic microscope. The feasibility of multiple-sided Cu–Sn TLP bonding is demonstrated by the absence of bondline damage in multiple test samples fabricated with double- or four-sided bonding using the TLP bonding process.

https://iopscience.iop.org/article/10.1088/0960-1317/23/1/015017/pdf

Reliable and repeatable bonding technology for high temperature automotive power modules for electrified vehicles

A traditional power module uses metal clad ceramic (e.g. DBC or DBA) bonded to a baseplate that creates a highly thermally resistive path, and wire bond interconnect that introduces substantial inductance and limits thermal management to single-sided cooling. This paper introduces a Power Chip on Bus (PCoB) power module approach that reduces parasitic inductance through an integrated power interconnect structure. The PCoB maximizes thermal performance by direct attaching power chips to the busbar, integrating the heatsink and busbar as one, and uses a dielectric fluid, such as air, for electrical isolation. This new power module topology features all planar interconnects and double-sided air cooling. Performance evaluations are carried out through comprehensive electrical and multi-physics simulation and thermal testing for a 1200V, 100A rated single-switch PCoB design. Fabrication and assembly processes are included. For the developed double-sided air-cooled module, 0.5°C/w thermal resistance and 8nH power loop parasitic inductance are achieved.

Development of an ultra-high density Power Chip on Bus (PCoB) module

A new approach to packaging high performance power devices, Chip on Flex Power Overlay (POL) was presented. It was shown that the GE's cost effective POL power packaging technology is ideally suited for high heat flux and high performance applications. This is primarily due to the elimination of bond wires and the planar geometry which offers cooling of power devices from top, bottom or both sides of the power module. It was also shown that a cost effective, scalable high performance integral heat exchanger can maximize the thermal performance of POL technology thereby helping to utilize its full potential. Due to the excellent thermal and electrical performance, low weight, volume, and cost effectiveness GE's revolutionary POL technology sets a new standard for the future of packaging power electronics modules.

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P. McConnelee

Papers

A new power module packaging technology for enhanced thermal performance