P. P. Rajeevan

Bio: P. P. Rajeevan is an academic researcher from Indian Institute of Science. The author has contributed to research in topics: Induction motor & Inverter. The author has an hindex of 8, co-authored 13 publications receiving 590 citations.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

Abstract: In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

A Nine-Level Inverter Topology for Medium-Voltage Induction Motor Drive With Open-End Stator Winding

Abstract: A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected $H$ -bridges. The $H$ -bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the $H$ -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

Abstract: This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

A Space-Vector-Based Hysteresis Current Controller for a General n-Level Inverter-Fed Drive With Nearly Constant Switching Frequency Control

Abstract: A current-error space-vector-based hysteresis current controller for a general n-level voltage-source inverter (VSI)-fed three-phase induction motor (IM) drive is proposed here, with control of the switching frequency variation for the full linear modulation range. The proposed current controller monitors the space-vector-based current error of an n -level VSI-fed IM to keep the current error within a parabolic boundary, using the information of the current triangular sector in which the tip of the reference vector lies. Information of the reference voltage vector is estimated using the measured current-error space vectors, along the α - and β-axes. Appropriate dimension and orientation of this parabolic boundary ensure a switching frequency spectrum similar to that of a constant-switching-frequency voltage-controlled space vector pulsewidth modulation (PWM) (SVPWM)-based IM drive. Like SVPWM for multilevel inverters, the proposed controller selects inverter switching vectors, forming a triangular sector in which the tip of the reference vector stays, for the hysteresis PWM control. The sector in the n-level inverter space vector diagram, in which the tip of the fundamental stator voltage stays, is precisely detected, using the sampled reference space vector estimated from the instantaneous current-error space vectors. The proposed controller retains all the advantages of a conventional hysteresis controller such as fast current control, with smooth transition to the overmodulation region. The proposed controller is implemented on a five-level VSI-fed 7.5-kW IM drive.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

Abstract: A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating Vdc/2 where Vdc is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of Vdc/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of Vdc /2, switch less compared to the H-bridges, which operate at a lower voltage level of Vdc/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Multi-level conversion : high voltage choppers and voltage-source inverters

Abstract: The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<>

Hybrid Multilevel Inverter Using Switched Capacitor Units

Abstract: In this paper, two new topologies are proposed for multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter units. The proposed topologies reduce the number of switches and isolated dc voltage sources, the variety of the dc voltage source values, and the size and cost of the system in comparison with the conventional topologies. In addition, the proposed topologies can double the input voltage without a transformer. There is no need for complicated methods to balance the capacitor voltage. The simulation and experimental results of single-phase 25- and 17-level inverters are given to prove the correct operation of the proposed topologies.

Deadbeat Predictive Current Control of Permanent-Magnet Synchronous Motors with Stator Current and Disturbance Observer

Abstract: In order to optimize the current-control performance of the permanent-magnet synchronous motor (PMSM) system with model parameter mismatch and one-step control delay, an improved deadbeat predictive current control (DPCC) algorithm for the PMSM drive systems is proposed in this paper. First, the performance of the conventional predictive current control, when parameter mismatch exist, is analyzed, and then a stator current and disturbance observer (SCDO) based on sliding-mode exponential reaching law, which is able to simultaneously predict future value of stator current and track system disturbance caused by parameter mismatch in real time, is proposed. Based on this SCDO, prediction currents are used for replacing the sampled current in DPCC to compensate one-step delay, and estimated parameter disturbances are considered as the feedforward value to compensate the voltage reference calculated by deadbeat predictive current controller. Thus, a composite control method combining the DPCC part and current prediction and feedforward compensation part based on SCDO, called DPCC + SCDO method, is developed. Moreover, based on conventional exponential reaching law, a novel sliding-mode exponential reaching law is proposed to further improve the performance of the DPCC + SCDO method. Simulation and experimental results both show the validity of the proposed current control approach.

A step-up switched-capacitor multilevel inverter with self-voltage balancing

Abstract: The objective of this paper is to propose a new inverter topology for a multilevel voltage output. This topology is designed based on a switched capacitor (SC) technique, and the number of output levels is determined by the number of SC cells. Only one dc voltage source is needed, and the problem of capacitor voltage balancing is avoided as well. This structure is not only very simple and easy to be extended to a higher level, but also its gate driver circuits are simplified because the number of active switches is reduced. The operational principle of this inverter and the targeted modulation strategies are presented, and power losses are investigated. Finally, the performance of the proposed multilevel inverter is evaluated with the experimental results of an 11-level prototype inverter.

A Simplified Nearest Level Control (NLC) Voltage Balancing Method for Modular Multilevel Converter (MMC)

Abstract: In this paper, a simplified nearest level control balancing method for modular multilevel converter is presented. The proposed method neither requires individual sorting of the submodule voltages nor the redundancy of the switching states. Once the sorting of the submodules is done on the basis of the number of the submodules to be switched on, the identifications of the submodules can be carried out throughout the stages of the implementation of the this method. The proposed method also does not require the individual submodule status in the gate pulse generation stage. The gate logic in the presented method can be implemented with the help of the switching states of the voltage levels. Those simplifications and removing of the some of the stages by the proposed balancing method may ease and lead to the less processor time at the implementation level. The pictorial presentation further helps in consolidating the understanding of the different stages of the method. Rigorous simulations are carried out for open and one of the prominent closed-loop applications, i.e., modular multilevel converter-based high-voltage direct current to demonstrate the validity and effectiveness of the proposed simplified balancing method under normal and emergency conditions.