P. Palanivel

Bio: P. Palanivel is an academic researcher from M.A.M College of Engineering. The author has contributed to research in topics: Pulse-width modulation & Total harmonic distortion. The author has an hindex of 6, co-authored 15 publications receiving 253 citations. Previous affiliations of P. Palanivel include SRM University & Adama University.

Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques

Abstract: Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.

Multicarrier pulse width modulation methods based three phase cascaded multilevel inverter including over modulation and low modulation indices

Abstract: The multilevel inverter utilization have been increased since the last decade. These new type of inverters are suitable in various high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum and faithful output. This paper presents, two proposed scheme adopting the multicarrier Pulse width modulation concept. The multicarrier pulse width modulation Cascaded multilevel inverter strategy enhances the fundamental output voltage and reduced total harmonic distortion. The multilevel inverter circuit analysis and selection of proper references discussed based on the formulation switching patterns. A Three phase five level cascaded inverter is used to explain the methods. The methods can be easily extended to a n-level inverter. The cascaded inverter is subjected to a new modulation scheme, which uses multiple modulating signals with a single carrier. From the modulation scheme, mathematical equations that define the pulse width modulation switching instants are derived. In order to justify the merits of the proposed modulation scheme, harmonic analysis for and measured Total harmonic distortion and output voltages are compared and discussed. The method can be confirmed by experimental results obtained using a three phase cascaded five level inverter.

A FPGA based Variable switching frequency Multi-carrier Pulse width modulation for Three phase Multilevel Inverter

Abstract: This Paper presents, a Variable switching frequency Multi-carrier Pulse width modulation (VSFMC PWM) is proposed which can reduces the output Total harmonic distortion (THD) and increases the output Voltage from five level to multi level topologies. Multi level inverters are important for Power electronics applications such as active power filers, uninterruptible power supplies and renewable energy sources. Two noval methodologies adopting the Variable switching frequency Multi-carrier Pulse width modulation concept are proposed. The VSFMC-SH PWM Cascaded Multilevel Inverter strategy reduced output Total harmonic distortion and VSFMC-SFO PWM Cascaded Multilevel Inverter strategy enhances the output Voltages. Field programmable gate array ( FPGA ) has been chosen to implement the Pulse width modulation due its fast proto typing, simple hardware and software design. Simulation and Experimental results are provided.

Design and Development of Energy Management System for DG Source Allocation in a Micro Grid with Energy Storage System

Abstract: This paper proposes an Energy Management System (EMS) with fuzzy logic controller for a grid connected hybrid power system. Modeling and simulation are implemented using MATLAB/SIMULINK package. The objective of proposed EMS for micro grid with battery storage system is to optimize the fuel cost, improving the energy utilization efficiency and to manage the peak load demand by scheduling the generation according to the availability of the fuel. The proposed energy management algorithm for grid connected hybrid energy system helps integration of PV panels and wind power in to the grid which manage the peak load demand, and also it improves the stability of the system under different transient conditions by maintaining the frequency and voltage close to the nominal value for different load. The simulation results of proposed EMS using fuzzy logic expert system shows the minimization on the operating cost and emission level of micro grid by optimal scheduling of power generation ,and maintains the State of Charge (SOC) of batteries in desired value which improves the battery life. The proposed multi objective intelligent energy management system offers a proper tool for improving the system reliability and operational efficiency of a micro grid.

A Fault-Tolerant Single-Phase Five-Level Inverter for Grid-Independent PV Systems

Abstract: In this paper, a fault-tolerant single-phase five-level inverter configuration is proposed for photovoltaic (PV) generation systems. Conventional two-level inverters are popularly used in PV applications, but these inverters provide the output voltage with considerable harmonic content. One of the efficient ways to improve the power quality of PV generation systems is to replace a two-level inverter with a multilevel inverter. Conventional multilevel inverters reduce total harmonic distortion and filter requirements effectively, but it has limitations in terms of reliability due to increased device count and capacitor voltage balancing issues. Therefore, a fault-tolerant single-phase five-level inverter is presented, which is constructed by using a half-bridge two-level inverter, a three-level diode clamp inverter, and a bidirectional switch. The proposed inverter topology can tolerate the system faults due to failure of the source and/or switching devices with least modification in the switching combinations. It has less number of switching devices compared to conventional five-level inverters. The topology also has the energy-balancing capability between sources which helps in reducing uneven charge of batteries in case of partial shading or hotspots on one side of the PV panels. The proposed system under normal and faulty condition is simulated in MATLAB/Simulink environment, and results are verified with a laboratory prototype.

Review on pulse-width modulation strategies for common-mode voltage reduction in three-phase voltage-source inverters

Abstract: With wide application of inverters in modern industry, common-mode voltage (CMV) problems invoked severe negative effects. Hardware and software solutions have been proposed to reduce the CMV. Compared with hardware CMV mitigation solutions, software strategies based on pulse-width modulation (PWM) modifications have aroused widespread attention for their cost-effective and control flexible advantages. Up to date, various reduced CMV PWM (RCMV-PWM) strategies have been reported, such as active zero state PWM, remote state PWM, near state PWM, phase-shifted carrier PWM, carrier peak position modulation and so on. For convenience of understanding and utilising the existed RCMV-PWM strategies, this study conducts a review on this topic. According to the principle of CMV reduction algorithms, the study divides the reported RCMV-PWM strategies into three different categories. It also presents comparisons of CMV reduction techniques and output performances (like CMV value, output ripple and linearity range) between different strategies. Meanwhile, CMV suppression principles, problems in implementation and improvements of each technique are described in detail. Moreover, the inherent characteristics and development tendencies of the RCMV-PWM techniques are discussed so as to offer reference for further research.

Reviews on multilevel converter and modulation techniques

Abstract: The multilevel converter, (MC) had been recommended for high- and medium-level power applications for decades. It is one of the most popular converters due to its ability to decrease the harmonic distortion in the output waveform without decreasing the converter power output. This paper presents the basic concept of four different types of multilevel converter: the neutral-point clamped, flying capacitor, cascaded H-bridge and modular. This paper also reviews five different modulation techniques for multilevel converters: pulse width modulation, space vector pulse width modulation, phase shifted carrier pulse width modulation, sinusoidal pulse width modulation and selective harmonic elimination pulse width modulation. In addition, recent publications regarding developments and improvements of fundamental concern to MCs and modulation techniques are reviewed in this paper. The implementation of MCs within renewable energy systems is also discussed here.

Hybrid topology of symmetrical multilevel inverter using less number of devices

Abstract: The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

Carrier-Based Neutral Point Potential Regulator With Reduced Switching Losses for Three-Level Diode-Clamped Inverter

Abstract: This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles.