P. S. T. N. Srinivas

Bio: P. S. T. N. Srinivas is an academic researcher from Indian Institute of Technology Patna. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 1, co-authored 1 publications receiving 7 citations.

Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)

Abstract: In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the effect of substrate-induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. Such changes render difference in potential between substrate bulk and surface. The channel potential has been modelled using the parabolic approximation method. The developed model is useful for the optimization of short-channel effects for SOI JLFETs. The substrate bias voltage as a fourth terminal is found to be a powerful tool for tuning the threshold voltage for different device parameters variation. The model results are in good agreement with the simulation results obtained from Sentaurus TCAD simulator.

Analytical Model Development for Channel Potential in Junction-less Double-Gate FETs

Abstract: An analytical-model for potential- distribution in channel region of Junctionless-Double-Gate FETs by considering Gaussian-like vertical doping is introduced in this manuscript. To calculate the channel-potential distribution in the channel region, the two-dimensional Poisson’s-equation is derived by including the evanescent kind technique. The channel conduction-path position also been modelled to derive the channel-potential at various points in the channel conduction route. The channel potential considered to be the addition of the conventional device potential obtained by Poisson’s solution and the potential function calculated by Laplace equation. The strength of the developed model is verified by relating with physics based arithmetic simulation results attained by commercially accessible ATLAS TCAD tool and found in good agreement.

Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET)

Abstract: In the present article, the modeling of subthreshold current of asymmetric silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) is done. The switching properties are further investigated by formulating the subthreshold swing characteristics based on the minimum potential concept. The model adopts the effect of substrate-induced surface potential (SISP) effect as well as source/drain depletion region with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. The developed model is beneficial for the optimization of low power switching characteristics for SOI JLFETs. The model results are validated with the numerical simulation results obtained from Sentaurus TCAD simulator.

Threshold-Voltage Analytical-Model Development for Junction-less-Double-Gate FETs

Abstract: A threshold voltage analytical model for Junctionless Double-Gate FETs by considering Gaussian-like vertical doping is shown in this article. To calculate the threshold voltage, first, the two-dimensional Poisson's equation is derived by including the evanescent-mode technique to calculate distribution channel potential in the channel region. The channel potential is considered to be the addition of the conventional device potential obtained by Poisson's solution and the potential function calculated by Laplace equation. Then, the calculated channel potential function has been incorporated in modelling the threshold voltage. The validity of the developed models is verified by comparing with physics based numerical TCAD simulation characteristics obtained by ATLAS TCAD tool and found in good agreement.

CJFET Differential Pairs’ Constructions and Characteristics for Design of Cbicjfet Differential Amplifiers and Differential Difference Amplifiers’

Abstract: We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.