P. Salija

Bio: P. Salija is an academic researcher from Amrita Vishwa Vidyapeetham. The author has contributed to research in topics: Turbo code & Error detection and correction. The author has an hindex of 1, co-authored 2 publications receiving 2 citations.

Performance Analysis of Reliability-Based Decoding Algorithm for Short Block Length Turbo Codes

Abstract: Demand for transmission using short block length messages has been increased recently in applications including satellite communication, mobile communication, wireless sensor networks, and machine ...

Effect of sign-bit-flipping trojan on turbo coded communication systems

Abstract: In complex systems like 'Internet of Things' and 'Cyber Physical Systems', reliable communication is made possible by the use of error control codes like turbo codes. Such systems are vulnerable to attack by Trojans during the design or fabrication phases of IC manufacturing. This leads to a severe performance degradation of the entire system. This paper aims at analyzing the effect of a sign-bit-flipping Trojan on a turbo coded communication system. Simulations were carried out on a conventional iterative turbo decoder and the results point out that the Trojan affects the performance of the decoder at SNRs greater than -2 dB. This performance degradation is seen even with minimal activation of the Trojan and a finite error persists even at very high SNRs.

A comparison analysis on forward error correction technology: a future perspective for GNSS

Abstract: Purpose The main aim of this study is to elaborately examine the error correction technology for global navigation satellite system (GNSS) navigation messages and to draw a conceptual decision support framework related to the modernization of the GNSS and other systems. Design/methodology/approach The extensive simulation model developed in Matrix Laboratory (MATLAB) is used to evaluate the performance of forward error correction (FEC) codes such as Hamming, Bose–Chaudhuri–Hocquenghem, convolutional, turbo, low-density parity check (LDPC) and polar codes under different levels of noise. Findings The performance and robustness of the aforementioned algorithms are compared based on the bit length, complexity and execution time of the GNSS navigation message. In terms of bit error rate, LDPC coding exhibits more ability in the robustness of the navigation message, while polar code gives better results according to the execution time. Practical implications In view of future new GNSS signals and message design, the findings of this paper may provide significant insight into navigation message modernization and design as an important part of GNSS modernization. Originality/value To the best of the authors’ knowledge, this is the first study that conducts a direct comparison of various FEC algorithms on GNSS navigation message performance against noise, taking into consideration turbo and newly developed polar codes.

Generic Direct Approach for Decoding Turbo Codes Using Probability Density Based Reliability Model

Abstract: The probability of the received bit values has been directly used in the performance enhanced reliability based direct decoding algorithm for turbo codes proposed recently and has achieved a significant coding gain improvement. This is in contrast to the maximum a posteriori (MAP)—type decoders and their variants in vogue which use log-likelihood ratio (LLR) in place of reliability and go through an iterative process. In this paper reliability has been identified in terms of probability densities of the bit values and the same used with the direct decoding algorithm. Extensive simulations with commonly used encoders show a clear performance improvement especially for short block lengths. Neither does the approach constrain noise distribution in any way as brought out by considering different distributions.

Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores

Abstract: Existing techniques to ensure functional correctness and hardware trust during pre-silicon verification face severe limitations. In this work, we systematically leverage two key ideas: 1) Symbolic Quick Error Detection (Symbolic QED or SQED), a recent bug detection and localization technique using Bounded Model Checking (BMC); and 2) Symbolic starting states, to present a method that: i) Effectively detects both "difficult" logic bugs and Hardware Trojans, even with long activation sequences where traditional BMC techniques fail; and ii) Does not need skilled manual guidance for writing testbenches, writing design-specific assertions, or debugging spurious counter-examples. Using open-source RISC-V cores, we demonstrate the following: 1. Quick (<5 minutes for an in-order scalar core and <2.5 hours for an out-of-order superscalar core) detection of 100% of hundreds of logic bug and hardware Trojan scenarios from commercial chips and research literature, and 97.9% of "extremal" bugs (randomly-generated bugs requiring ~100,000 activation instructions taken from random test programs). 2. Quick (~1 minute) detection of several previously unknown bugs in open-source RISC-V designs.